
Daniel S. Collins
Examiner (ID: 1085, Phone: (313)446-6535 , Office: P/3745 )
| Most Active Art Unit | 3745 |
| Art Unit(s) | 3745 |
| Total Applications | 854 |
| Issued Applications | 696 |
| Pending Applications | 75 |
| Abandoned Applications | 98 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6078191
[patent_doc_number] => 20110141824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-16
[patent_title] => 'LEAKAGE COMPENSATED REFERENCE VOLTAGE GENERATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/639454
[patent_app_country] => US
[patent_app_date] => 2009-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0141/20110141824.pdf
[firstpage_image] =>[orig_patent_app_number] => 12639454
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/639454 | Leakage compensated reference voltage generation system | Dec 15, 2009 | Issued |
Array
(
[id] => 6194565
[patent_doc_number] => 20110026319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT AND METHOD OF CONTROLLING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/636894
[patent_app_country] => US
[patent_app_date] => 2009-12-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0026/20110026319.pdf
[firstpage_image] =>[orig_patent_app_number] => 12636894
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/636894 | Non-volatile semiconductor memory circuit and method of controlling the same | Dec 13, 2009 | Issued |
Array
(
[id] => 6210805
[patent_doc_number] => 20110134685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-09
[patent_title] => 'Energy-efficient set write of phase change memory with switch'
[patent_app_type] => utility
[patent_app_number] => 12/653092
[patent_app_country] => US
[patent_app_date] => 2009-12-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0134/20110134685.pdf
[firstpage_image] =>[orig_patent_app_number] => 12653092
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/653092 | Energy-efficient set write of phase change memory with switch | Dec 7, 2009 | Issued |
Array
(
[id] => 6628141
[patent_doc_number] => 20100226193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-09
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/633238
[patent_app_country] => US
[patent_app_date] => 2009-12-08
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12633238
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/633238 | SEMICONDUCTOR MEMORY DEVICE | Dec 7, 2009 | Abandoned |
Array
(
[id] => 6180936
[patent_doc_number] => 20110122675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-26
[patent_title] => 'Programmable Resistance Memory'
[patent_app_type] => utility
[patent_app_number] => 12/626234
[patent_app_country] => US
[patent_app_date] => 2009-11-25
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[firstpage_image] =>[orig_patent_app_number] => 12626234
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/626234 | Programmable Resistance Memory | Nov 24, 2009 | Abandoned |
Array
(
[id] => 6181016
[patent_doc_number] => 20110122692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-26
[patent_title] => 'PROGRAMMING NON-VOLATILE MEMORY WITH A REDUCED NUMBER OF VERIFY OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 12/625883
[patent_app_country] => US
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[pdf_file] => publications/A1/0122/20110122692.pdf
[firstpage_image] =>[orig_patent_app_number] => 12625883
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/625883 | Programming non-volatile memory with a reduced number of verify operations | Nov 24, 2009 | Issued |
Array
(
[id] => 6181047
[patent_doc_number] => 20110122702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-26
[patent_title] => 'PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING'
[patent_app_type] => utility
[patent_app_number] => 12/624595
[patent_app_country] => US
[patent_app_date] => 2009-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[pdf_file] => publications/A1/0122/20110122702.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624595
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624595 | Programming memory with sensing-based bit line compensation to reduce channel-to-floating gate coupling | Nov 23, 2009 | Issued |
Array
(
[id] => 6508443
[patent_doc_number] => 20100202221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-12
[patent_title] => 'METHOD OF READING MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 12/624403
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0202/20100202221.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624403
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624403 | METHOD OF READING MEMORY CELL | Nov 22, 2009 | Abandoned |
Array
(
[id] => 8271712
[patent_doc_number] => 08213224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'High density low power nanowire phase change material memory device'
[patent_app_type] => utility
[patent_app_number] => 12/624141
[patent_app_country] => US
[patent_app_date] => 2009-11-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624141 | High density low power nanowire phase change material memory device | Nov 22, 2009 | Issued |
Array
(
[id] => 8593371
[patent_doc_number] => 08351248
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-01-08
[patent_title] => 'CMOS SRAM memory cell with improved N/P current ratio'
[patent_app_type] => utility
[patent_app_number] => 12/624291
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624291 | CMOS SRAM memory cell with improved N/P current ratio | Nov 22, 2009 | Issued |
Array
(
[id] => 5489196
[patent_doc_number] => 20090290267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'Magnetic Recording and Reproducing Apparatus with Thin-Film Magnetic Head Having Microwave Magnetic Exciting Function'
[patent_app_type] => utility
[patent_app_number] => 12/470150
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/470150 | Magnetic recording and reproducing apparatus with thin-film magnetic head having microwave magnetic exciting function | May 20, 2009 | Issued |
Array
(
[id] => 6228184
[patent_doc_number] => 20100058369
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[patent_issue_date] => 2010-03-04
[patent_title] => 'OPTICAL DISK APPARATUS'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 12468111
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/468111 | OPTICAL DISK APPARATUS | May 18, 2009 | Abandoned |
Array
(
[id] => 8307075
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[patent_title] => 'Conductive paths in a hard disk drive enclosure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/467176 | Conductive paths in a hard disk drive enclosure | May 14, 2009 | Issued |
Array
(
[id] => 8665876
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[patent_issue_date] => 2013-02-19
[patent_title] => 'Airflow dispersion system'
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Array
(
[id] => 6570066
[patent_doc_number] => 20100290161
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[patent_title] => 'LATCH ASSEMBLY FOR A HEAD OR HEAD ASSEMBLY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/465026 | Latch assembly for a head or head assembly | May 12, 2009 | Issued |
Array
(
[id] => 5314611
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[patent_title] => 'Magnetic Head Suspension'
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/453208 | Fluid dynamic bearing unit and disk drive device including the same | Apr 30, 2009 | Issued |
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/431679 | Head driving device and disk apparatus | Apr 27, 2009 | Issued |