Search

Daniel S. Collins

Examiner (ID: 173, Phone: (313)446-6535 , Office: P/3745 )

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
779
Issued Applications
623
Pending Applications
71
Abandoned Applications
85
Applications
StatisticsSubscription-Only

Applications

Application numberTitle of the applicationFiling DateStatus
08/245504 POLYSILICON PROGRAMMING MEMORY CELL May 17, 1994 Abandoned
08/242695 MULTISTATE ROM MEMORY CELL ARRAY May 12, 1994 Abandoned
Array ( [id] => 3697948 [patent_doc_number] => 05691938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Non-volatile memory cell and array architecture' [patent_app_type] => 1 [patent_app_number] => 8/237226 [patent_app_country] => US [patent_app_date] => 1994-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 6385 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691938.pdf [firstpage_image] =>[orig_patent_app_number] => 237226 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237226 		Non-volatile memory cell and array architecture May 2, 1994 Issued
08/237225 DYNAMIC ASSOCIATIVE MEMORY WITH LOGIC-IN-REFRESH May 1, 1994 Abandoned
Array ( [id] => 3130572 [patent_doc_number] => 05381366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Non-volatile semiconductor memory device with timer controlled re-write inhibit means' [patent_app_type] => 1 [patent_app_number] => 8/236002 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4178 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381366.pdf [firstpage_image] =>[orig_patent_app_number] => 236002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/236002 		Non-volatile semiconductor memory device with timer controlled re-write inhibit means May 1, 1994 Issued
Array ( [id] => 3600727 [patent_doc_number] => 05488579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Three-dimensionally integrated nonvolatile SRAM cell and process' [patent_app_type] => 1 [patent_app_number] => 8/235735 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4425 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488579.pdf [firstpage_image] =>[orig_patent_app_number] => 235735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/235735 		Three-dimensionally integrated nonvolatile SRAM cell and process Apr 28, 1994 Issued
Array ( [id] => 3600727 [patent_doc_number] => 05488579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Three-dimensionally integrated nonvolatile SRAM cell and process' [patent_app_type] => 1 [patent_app_number] => 8/235735 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4425 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488579.pdf [firstpage_image] =>[orig_patent_app_number] => 235735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/235735 		Three-dimensionally integrated nonvolatile SRAM cell and process Apr 28, 1994 Issued
Array ( [id] => 3498812 [patent_doc_number] => 05471419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Semiconductor device having a programmable memory cell' [patent_app_type] => 1 [patent_app_number] => 8/231860 [patent_app_country] => US [patent_app_date] => 1994-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4447 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471419.pdf [firstpage_image] =>[orig_patent_app_number] => 231860 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231860 		Semiconductor device having a programmable memory cell Apr 21, 1994 Issued
08/229155 SEMICONDUCTOR INTEGRATED CIRCUIT Apr 17, 1994 Abandoned
08/226485 SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL BIT LINE ARRANGEMENT Apr 11, 1994 Abandoned
08/224015 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF USING THE SAME Apr 5, 1994 Abandoned
Array ( [id] => 3116851 [patent_doc_number] => 05418738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Low voltage programmable storage element' [patent_app_type] => 1 [patent_app_number] => 8/221515 [patent_app_country] => US [patent_app_date] => 1994-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5039 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418738.pdf [firstpage_image] =>[orig_patent_app_number] => 221515 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/221515 		Low voltage programmable storage element Mar 31, 1994 Issued
Array ( [id] => 3467349 [patent_doc_number] => 05473564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Memory card having an integrated circuit for the secure counting down of units' [patent_app_type] => 1 [patent_app_number] => 8/221166 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5357 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473564.pdf [firstpage_image] =>[orig_patent_app_number] => 221166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/221166 		Memory card having an integrated circuit for the secure counting down of units Mar 30, 1994 Issued
08/219534 NON-VOLATILE MEMORY DEVICE Mar 28, 1994 Abandoned
08/215241 PASS TRANSISTOR FOR A 256 MEGABIT DRAM WITH NEGATIVELY BIASED SUBSTRATE Mar 20, 1994 Abandoned
Array ( [id] => 3497670 [patent_doc_number] => 05475640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method and apparatus for inhibiting a predecoder when selecting a redundant row line' [patent_app_type] => 1 [patent_app_number] => 8/215554 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5884 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475640.pdf [firstpage_image] =>[orig_patent_app_number] => 215554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/215554 		Method and apparatus for inhibiting a predecoder when selecting a redundant row line Mar 20, 1994 Issued
Array ( [id] => 3835930 [patent_doc_number] => 05732012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Rom cell with reduced drain capacitance' [patent_app_type] => 1 [patent_app_number] => 8/210595 [patent_app_country] => US [patent_app_date] => 1994-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 917 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732012.pdf [firstpage_image] =>[orig_patent_app_number] => 210595 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/210595 		Rom cell with reduced drain capacitance Mar 16, 1994 Issued
08/213215 VIRTUAL-GROUND FLASH EPROM ARRAY WITH REDUCED CELL PITCH IN THE X DIRECTION Mar 14, 1994 Abandoned
08/213474 CONTENT ADDRESSABLE MEMORY Mar 14, 1994 Abandoned
Array ( [id] => 3664464 [patent_doc_number] => 05623443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Scalable EPROM array with thick and thin non-field oxide gate insulators' [patent_app_type] => 1 [patent_app_number] => 8/212165 [patent_app_country] => US [patent_app_date] => 1994-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5847 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623443.pdf [firstpage_image] =>[orig_patent_app_number] => 212165 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/212165 		Scalable EPROM array with thick and thin non-field oxide gate insulators Mar 10, 1994 Issued
Menu