Search

Daniel V. Venne

Examiner (ID: 394)

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
2006
Issued Applications
1406
Pending Applications
132
Abandoned Applications
502

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7486172 [patent_doc_number] => 20110250741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus' [patent_app_type] => utility [patent_app_number] => 13/067638 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6227 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250741.pdf [firstpage_image] =>[orig_patent_app_number] => 13067638 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067638
Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus Jun 15, 2011 Issued
Array ( [id] => 8642499 [patent_doc_number] => 08367482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Methods for fabricating contacts of semiconductor device structures and methods for designing semiconductor device structures' [patent_app_type] => utility [patent_app_number] => 13/113468 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 5230 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13113468 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/113468
Methods for fabricating contacts of semiconductor device structures and methods for designing semiconductor device structures May 22, 2011 Issued
Array ( [id] => 6084806 [patent_doc_number] => 20110215863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Integrated Voltage Regulator with Embedded Passive Device(s)' [patent_app_type] => utility [patent_app_number] => 13/108335 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20110215863.pdf [firstpage_image] =>[orig_patent_app_number] => 13108335 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/108335
Integrated Voltage Regulator with Embedded Passive Device(s) May 15, 2011 Abandoned
Array ( [id] => 8480924 [patent_doc_number] => 20120280331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Adaptive Fin Design for FinFETs' [patent_app_type] => utility [patent_app_number] => 13/101890 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3970 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/101890
Adaptive fin design for FinFETs May 4, 2011 Issued
Array ( [id] => 8483337 [patent_doc_number] => 20120282744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Reduced Threshold Voltage-Width Dependency and Reduced Surface Topography in Transistors Comprising High-K Metal Gate Electrode Structures by a Late Carbon Incorporation' [patent_app_type] => utility [patent_app_number] => 13/101764 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9535 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101764 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/101764
Reduced threshold voltage-width dependency and reduced surface topography in transistors comprising high-k metal gate electrode structures by a late carbon incorporation May 4, 2011 Issued
Array ( [id] => 8738180 [patent_doc_number] => 08409950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-02 [patent_title] => 'Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow' [patent_app_type] => utility [patent_app_number] => 13/100986 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3863 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100986 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100986
Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow May 3, 2011 Issued
Array ( [id] => 7561337 [patent_doc_number] => 20110275170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SYSTEM FOR CONCURRENT TEST OF SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/100889 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 23133 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20110275170.pdf [firstpage_image] =>[orig_patent_app_number] => 13100889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100889
System for concurrent test of semiconductor devices May 3, 2011 Issued
Array ( [id] => 8386089 [patent_doc_number] => 08263485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/100197 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5966 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100197
Method for fabricating semiconductor device May 2, 2011 Issued
Array ( [id] => 6047716 [patent_doc_number] => 20110207265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'Nonvolatile memory devices and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/064960 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5746 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20110207265.pdf [firstpage_image] =>[orig_patent_app_number] => 13064960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064960
Nonvolatile memory devices and method of manufacturing the same Apr 27, 2011 Abandoned
Array ( [id] => 6161334 [patent_doc_number] => 20110193189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 13/087703 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5336 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193189.pdf [firstpage_image] =>[orig_patent_app_number] => 13087703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/087703
Semiconductor substrate, method of fabricating the same, method of fabricating semiconductor device, and method of fabricating image sensor Apr 14, 2011 Issued
Array ( [id] => 8675358 [patent_doc_number] => 08383471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Self aligned sidewall gate GaN HEMT' [patent_app_type] => utility [patent_app_number] => 13/083916 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 33 [patent_no_of_words] => 3792 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13083916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/083916
Self aligned sidewall gate GaN HEMT Apr 10, 2011 Issued
Array ( [id] => 8439663 [patent_doc_number] => 20120256279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/081505 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13081505 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/081505
Method of gate work function adjustment and metal gate transistor Apr 6, 2011 Issued
Array ( [id] => 6177707 [patent_doc_number] => 20110121419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/021079 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6295 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121419.pdf [firstpage_image] =>[orig_patent_app_number] => 13021079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/021079
METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE Feb 3, 2011 Abandoned
Array ( [id] => 8499644 [patent_doc_number] => 20120299052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND OPTICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/576954 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 24145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13576954 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/576954
SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND OPTICAL DEVICE Feb 3, 2011 Abandoned
Array ( [id] => 6177675 [patent_doc_number] => 20110121397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS' [patent_app_type] => utility [patent_app_number] => 13/021403 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121397.pdf [firstpage_image] =>[orig_patent_app_number] => 13021403 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/021403
Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods Feb 3, 2011 Issued
Array ( [id] => 6177595 [patent_doc_number] => 20110121358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'P-TYPE LAYER FOR A III-NITRIDE LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/017074 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4242 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121358.pdf [firstpage_image] =>[orig_patent_app_number] => 13017074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017074
P-TYPE LAYER FOR A III-NITRIDE LIGHT EMITTING DEVICE Jan 30, 2011 Abandoned
Array ( [id] => 8321394 [patent_doc_number] => 20120193807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE' [patent_app_type] => utility [patent_app_number] => 13/017682 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13017682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017682
DRAM cell based on conductive nanochannel plate Jan 30, 2011 Issued
Array ( [id] => 8920889 [patent_doc_number] => 08486822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Semiconductor device having dummy pattern and the method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/018358 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2421 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018358 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018358
Semiconductor device having dummy pattern and the method for fabricating the same Jan 30, 2011 Issued
Array ( [id] => 6055223 [patent_doc_number] => 20110111583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/010563 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10453 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20110111583.pdf [firstpage_image] =>[orig_patent_app_number] => 13010563 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/010563
Method of reducing coupling between floating gates in nonvolatile memory Jan 19, 2011 Issued
Array ( [id] => 6038975 [patent_doc_number] => 20110092024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/972963 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20110092024.pdf [firstpage_image] =>[orig_patent_app_number] => 12972963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/972963
Stacked semiconductor package and method for manufacturing the same Dec 19, 2010 Issued
Menu