
Daniel V. Venne
Examiner (ID: 394)
| Most Active Art Unit | 3617 |
| Art Unit(s) | 3617, 3615 |
| Total Applications | 2006 |
| Issued Applications | 1406 |
| Pending Applications | 132 |
| Abandoned Applications | 502 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 7480017
[patent_doc_number] => 20110248350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)'
[patent_app_type] => utility
[patent_app_number] => 12/757323
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/757323 | Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG) | Apr 8, 2010 | Issued |
Array
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[patent_title] => 'Vertical Stacking of Field Effect Transistor Structures for Logic Gates'
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Array
(
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[patent_doc_number] => 08410599
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[patent_issue_date] => 2013-04-02
[patent_title] => 'Power MOSFET package'
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Array
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[patent_issue_date] => 2013-10-15
[patent_title] => 'Thin film transistor substrate and method of fabricating the same'
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Array
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[patent_title] => 'Self-aligned contacts'
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[patent_title] => 'Semiconductor Device and Method for Manufacturing the Same'
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Array
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[patent_doc_number] => 20110241207
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[patent_title] => 'DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/753272 | Dummy shoulder structure for line stress reduction | Apr 1, 2010 | Issued |
Array
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[patent_issue_date] => 2014-03-04
[patent_title] => 'Dual sidewall spacer for seam protection of a patterned structure'
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[patent_app_number] => 12/751891
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/751891 | Dual sidewall spacer for seam protection of a patterned structure | Mar 30, 2010 | Issued |
Array
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[patent_title] => 'Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/750342 | Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain | Mar 29, 2010 | Issued |
Array
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[patent_title] => 'Sidewall-Free CESL for Enlarging ILD Gap-Fill Window'
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[patent_app_number] => 12/750485
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/750485 | Sidewall-Free CESL for Enlarging ILD Gap-Fill Window | Mar 29, 2010 | Abandoned |
Array
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[patent_doc_number] => 20110241118
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[patent_title] => 'METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE'
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Array
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Array
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