Search

Daniel V. Venne

Examiner (ID: 394)

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
2006
Issued Applications
1406
Pending Applications
132
Abandoned Applications
502

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7480017 [patent_doc_number] => 20110248350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)' [patent_app_type] => utility [patent_app_number] => 12/757323 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248350.pdf [firstpage_image] =>[orig_patent_app_number] => 12757323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757323
Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG) Apr 8, 2010 Issued
Array ( [id] => 7480015 [patent_doc_number] => 20110248349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Vertical Stacking of Field Effect Transistor Structures for Logic Gates' [patent_app_type] => utility [patent_app_number] => 12/757145 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3603 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248349.pdf [firstpage_image] =>[orig_patent_app_number] => 12757145 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757145
Vertical stacking of field effect transistor structures for logic gates Apr 8, 2010 Issued
Array ( [id] => 8738826 [patent_doc_number] => 08410599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Power MOSFET package' [patent_app_type] => utility [patent_app_number] => 12/756915 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7335 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12756915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756915
Power MOSFET package Apr 7, 2010 Issued
Array ( [id] => 9086800 [patent_doc_number] => 08558230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Thin film transistor substrate and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/756323 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9548 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12756323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756323
Thin film transistor substrate and method of fabricating the same Apr 7, 2010 Issued
Array ( [id] => 8807719 [patent_doc_number] => 08445371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Self-aligned contacts' [patent_app_type] => utility [patent_app_number] => 12/755752 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2350 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12755752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755752
Self-aligned contacts Apr 6, 2010 Issued
Array ( [id] => 6483573 [patent_doc_number] => 20100258802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Semiconductor Device and Method for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 12/754393 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11653 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258802.pdf [firstpage_image] =>[orig_patent_app_number] => 12754393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754393
Semiconductor device and method for manufacturing the same Apr 4, 2010 Issued
Array ( [id] => 8071633 [patent_doc_number] => 20110241207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION' [patent_app_type] => utility [patent_app_number] => 12/753272 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4933 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241207.pdf [firstpage_image] =>[orig_patent_app_number] => 12753272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753272
Dummy shoulder structure for line stress reduction Apr 1, 2010 Issued
Array ( [id] => 9344955 [patent_doc_number] => 08664102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Dual sidewall spacer for seam protection of a patterned structure' [patent_app_type] => utility [patent_app_number] => 12/751891 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5658 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751891
Dual sidewall spacer for seam protection of a patterned structure Mar 30, 2010 Issued
Array ( [id] => 9455084 [patent_doc_number] => 08716091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain' [patent_app_type] => utility [patent_app_number] => 12/750342 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3923 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12750342 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750342
Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain Mar 29, 2010 Issued
Array ( [id] => 6368762 [patent_doc_number] => 20100314690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'Sidewall-Free CESL for Enlarging ILD Gap-Fill Window' [patent_app_type] => utility [patent_app_number] => 12/750485 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314690.pdf [firstpage_image] =>[orig_patent_app_number] => 12750485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750485
Sidewall-Free CESL for Enlarging ILD Gap-Fill Window Mar 29, 2010 Abandoned
Array ( [id] => 8071803 [patent_doc_number] => 20110241118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE' [patent_app_type] => utility [patent_app_number] => 12/750340 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241118.pdf [firstpage_image] =>[orig_patent_app_number] => 12750340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750340
METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE Mar 29, 2010 Abandoned
Array ( [id] => 9233304 [patent_doc_number] => 08598612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Light emitting diode thermally enhanced cavity package and method of manufacture' [patent_app_type] => utility [patent_app_number] => 12/750426 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3285 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12750426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750426
Light emitting diode thermally enhanced cavity package and method of manufacture Mar 29, 2010 Issued
Array ( [id] => 6445414 [patent_doc_number] => 20100283084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'BIPOLAR TRANSISTOR AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/730878 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6003 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20100283084.pdf [firstpage_image] =>[orig_patent_app_number] => 12730878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/730878
BIPOLAR TRANSISTOR AND METHOD FOR FABRICATING THE SAME Mar 23, 2010 Abandoned
Array ( [id] => 6478105 [patent_doc_number] => 20100213491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'LIGHT-EMITTING DEVICE WITH NARROW DOMINANT WAVELENGTH DISTRIBUTION AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/711678 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3119 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20100213491.pdf [firstpage_image] =>[orig_patent_app_number] => 12711678 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711678
Light-emitting device with narrow dominant wavelength distribution and method of making the same Feb 23, 2010 Issued
Array ( [id] => 8528243 [patent_doc_number] => 08304815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Solid-state image pickup apparatus and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/660286 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 42 [patent_no_of_words] => 11719 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12660286 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/660286
Solid-state image pickup apparatus and method of manufacturing the same Feb 23, 2010 Issued
Array ( [id] => 6478105 [patent_doc_number] => 20100213491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'LIGHT-EMITTING DEVICE WITH NARROW DOMINANT WAVELENGTH DISTRIBUTION AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/711678 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3119 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20100213491.pdf [firstpage_image] =>[orig_patent_app_number] => 12711678 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711678
Light-emitting device with narrow dominant wavelength distribution and method of making the same Feb 23, 2010 Issued
Array ( [id] => 6427549 [patent_doc_number] => 20100151672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'METHODS OF FORMING METAL INTERCONNECTION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/711812 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5324 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20100151672.pdf [firstpage_image] =>[orig_patent_app_number] => 12711812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711812
Methods of forming metal interconnection structures Feb 23, 2010 Issued
Array ( [id] => 6517286 [patent_doc_number] => 20100230656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'LIGHT EMITTING STRUCTURE AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/705869 [patent_app_country] => US [patent_app_date] => 2010-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2481 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230656.pdf [firstpage_image] =>[orig_patent_app_number] => 12705869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705869
Light emitting structure and method of manufacture thereof Feb 14, 2010 Issued
Array ( [id] => 6058753 [patent_doc_number] => 20110198605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method' [patent_app_type] => utility [patent_app_number] => 12/704528 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20110198605.pdf [firstpage_image] =>[orig_patent_app_number] => 12704528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704528
Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method Feb 11, 2010 Issued
Array ( [id] => 4514304 [patent_doc_number] => 07910483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Trim process for critical dimension control for integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/698407 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 8240 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/910/07910483.pdf [firstpage_image] =>[orig_patent_app_number] => 12698407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698407
Trim process for critical dimension control for integrated circuits Feb 1, 2010 Issued
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