
Daniel V. Venne
Examiner (ID: 394)
| Most Active Art Unit | 3617 |
| Art Unit(s) | 3617, 3615 |
| Total Applications | 2006 |
| Issued Applications | 1406 |
| Pending Applications | 132 |
| Abandoned Applications | 502 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5262274
[patent_doc_number] => 20090114959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors'
[patent_app_type] => utility
[patent_app_number] => 12/153151
[patent_app_country] => US
[patent_app_date] => 2008-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5076
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20090114959.pdf
[firstpage_image] =>[orig_patent_app_number] => 12153151
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/153151 | Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors | May 13, 2008 | Issued |
Array
(
[id] => 8328497
[patent_doc_number] => 08236593
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Methods for improving the quality of epitaxially-grown semiconductor materials'
[patent_app_type] => utility
[patent_app_number] => 12/600120
[patent_app_country] => US
[patent_app_date] => 2008-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6960
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12600120
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/600120 | Methods for improving the quality of epitaxially-grown semiconductor materials | May 13, 2008 | Issued |
Array
(
[id] => 4960155
[patent_doc_number] => 20080274580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'METHOD FOR MANUFACTURING IMAGE SENSOR'
[patent_app_type] => utility
[patent_app_number] => 12/111995
[patent_app_country] => US
[patent_app_date] => 2008-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2434
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0274/20080274580.pdf
[firstpage_image] =>[orig_patent_app_number] => 12111995
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/111995 | METHOD FOR MANUFACTURING IMAGE SENSOR | Apr 29, 2008 | Abandoned |
Array
(
[id] => 4604714
[patent_doc_number] => 07985694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Method for forming pattern, method for manufacturing semiconductor device and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/101532
[patent_app_country] => US
[patent_app_date] => 2008-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 4755
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/985/07985694.pdf
[firstpage_image] =>[orig_patent_app_number] => 12101532
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/101532 | Method for forming pattern, method for manufacturing semiconductor device and semiconductor device | Apr 10, 2008 | Issued |
Array
(
[id] => 62790
[patent_doc_number] => 07763518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-27
[patent_title] => 'Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof'
[patent_app_type] => utility
[patent_app_number] => 12/099437
[patent_app_country] => US
[patent_app_date] => 2008-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 27
[patent_no_of_words] => 8000
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/763/07763518.pdf
[firstpage_image] =>[orig_patent_app_number] => 12099437
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/099437 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Apr 7, 2008 | Issued |
Array
(
[id] => 4495478
[patent_doc_number] => 07947521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-24
[patent_title] => 'Method for forming electrode for group-III nitride compound semiconductor light-emitting devices'
[patent_app_type] => utility
[patent_app_number] => 12/078066
[patent_app_country] => US
[patent_app_date] => 2008-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7857
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/947/07947521.pdf
[firstpage_image] =>[orig_patent_app_number] => 12078066
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/078066 | Method for forming electrode for group-III nitride compound semiconductor light-emitting devices | Mar 25, 2008 | Issued |
Array
(
[id] => 103047
[patent_doc_number] => 07728365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-01
[patent_title] => 'CMOS image sensor structure'
[patent_app_type] => utility
[patent_app_number] => 12/041672
[patent_app_country] => US
[patent_app_date] => 2008-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3002
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/728/07728365.pdf
[firstpage_image] =>[orig_patent_app_number] => 12041672
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/041672 | CMOS image sensor structure | Mar 3, 2008 | Issued |
Array
(
[id] => 5536792
[patent_doc_number] => 20090218597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-03
[patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME'
[patent_app_type] => utility
[patent_app_number] => 12/040562
[patent_app_country] => US
[patent_app_date] => 2008-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3264
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20090218597.pdf
[firstpage_image] =>[orig_patent_app_number] => 12040562
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/040562 | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same | Feb 28, 2008 | Issued |
Array
(
[id] => 7724675
[patent_doc_number] => 08097947
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-17
[patent_title] => 'Conductive systems and devices including wires coupled to anisotropic conductive film, and methods of forming the same'
[patent_app_type] => utility
[patent_app_number] => 12/039497
[patent_app_country] => US
[patent_app_date] => 2008-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 4965
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/097/08097947.pdf
[firstpage_image] =>[orig_patent_app_number] => 12039497
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/039497 | Conductive systems and devices including wires coupled to anisotropic conductive film, and methods of forming the same | Feb 27, 2008 | Issued |
Array
(
[id] => 7795719
[patent_doc_number] => 08124425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-28
[patent_title] => 'Method for manufacturing magnetic memory chip device'
[patent_app_type] => utility
[patent_app_number] => 12/525999
[patent_app_country] => US
[patent_app_date] => 2008-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 23
[patent_no_of_words] => 4325
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/124/08124425.pdf
[firstpage_image] =>[orig_patent_app_number] => 12525999
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/525999 | Method for manufacturing magnetic memory chip device | Feb 20, 2008 | Issued |
Array
(
[id] => 4951519
[patent_doc_number] => 20080184543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND STORAGE MEDIUM FOR EXECUTING THE METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/024445
[patent_app_country] => US
[patent_app_date] => 2008-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10891
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20080184543.pdf
[firstpage_image] =>[orig_patent_app_number] => 12024445
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/024445 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND STORAGE MEDIUM FOR EXECUTING THE METHOD | Jan 31, 2008 | Abandoned |
Array
(
[id] => 5377413
[patent_doc_number] => 20090189252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-30
[patent_title] => 'III-V MOSFET Fabrication and Device'
[patent_app_type] => utility
[patent_app_number] => 12/022942
[patent_app_country] => US
[patent_app_date] => 2008-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4189
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20090189252.pdf
[firstpage_image] =>[orig_patent_app_number] => 12022942
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/022942 | III-V MOSFET fabrication and device | Jan 29, 2008 | Issued |
Array
(
[id] => 4571145
[patent_doc_number] => 07829405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Lateral bipolar transistor with compensated well regions'
[patent_app_type] => utility
[patent_app_number] => 11/965935
[patent_app_country] => US
[patent_app_date] => 2007-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3681
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/829/07829405.pdf
[firstpage_image] =>[orig_patent_app_number] => 11965935
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/965935 | Lateral bipolar transistor with compensated well regions | Dec 27, 2007 | Issued |
Array
(
[id] => 4673409
[patent_doc_number] => 20080211037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Semiconductor Device and Method of Forming Isolation Layer Thereof'
[patent_app_type] => utility
[patent_app_number] => 11/962722
[patent_app_country] => US
[patent_app_date] => 2007-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2438
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0211/20080211037.pdf
[firstpage_image] =>[orig_patent_app_number] => 11962722
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962722 | Semiconductor Device and Method of Forming Isolation Layer Thereof | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4890818
[patent_doc_number] => 20080099915
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/953055
[patent_app_country] => US
[patent_app_date] => 2007-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8103
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20080099915.pdf
[firstpage_image] =>[orig_patent_app_number] => 11953055
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/953055 | Semiconductor device and a method of manufacturing the same | Dec 8, 2007 | Issued |
Array
(
[id] => 6430644
[patent_doc_number] => 20100152057
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-17
[patent_title] => 'HIGH-SENSITIVITY NANOSCALE WIRE SENSORS'
[patent_app_type] => utility
[patent_app_number] => 12/312740
[patent_app_country] => US
[patent_app_date] => 2007-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 22768
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20100152057.pdf
[firstpage_image] =>[orig_patent_app_number] => 12312740
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/312740 | High-sensitivity nanoscale wire sensors | Nov 18, 2007 | Issued |
Array
(
[id] => 4533221
[patent_doc_number] => 07888150
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'Display and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/985525
[patent_app_country] => US
[patent_app_date] => 2007-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 27
[patent_no_of_words] => 6775
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/888/07888150.pdf
[firstpage_image] =>[orig_patent_app_number] => 11985525
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/985525 | Display and method of manufacturing the same | Nov 13, 2007 | Issued |
Array
(
[id] => 4839954
[patent_doc_number] => 20080280440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-13
[patent_title] => 'METHOD FOR FORMING A PN DIODE AND METHOD OF MANUFACTURING PHASE CHANGE MEMORY DEVICE USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/938486
[patent_app_country] => US
[patent_app_date] => 2007-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3643
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0280/20080280440.pdf
[firstpage_image] =>[orig_patent_app_number] => 11938486
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/938486 | METHOD FOR FORMING A PN DIODE AND METHOD OF MANUFACTURING PHASE CHANGE MEMORY DEVICE USING THE SAME | Nov 11, 2007 | Abandoned |
Array
(
[id] => 43568
[patent_doc_number] => 07776662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'TFT LCD array substrate and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/935002
[patent_app_country] => US
[patent_app_date] => 2007-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 4200
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/776/07776662.pdf
[firstpage_image] =>[orig_patent_app_number] => 11935002
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/935002 | TFT LCD array substrate and manufacturing method thereof | Nov 4, 2007 | Issued |
Array
(
[id] => 11246375
[patent_doc_number] => 09472423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-18
[patent_title] => 'Method for suppressing lattice defects in a semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 11/928142
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1585
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11928142
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/928142 | Method for suppressing lattice defects in a semiconductor substrate | Oct 29, 2007 | Issued |