
Daniel V. Venne
Examiner (ID: 394)
| Most Active Art Unit | 3617 |
| Art Unit(s) | 3617, 3615 |
| Total Applications | 2006 |
| Issued Applications | 1406 |
| Pending Applications | 132 |
| Abandoned Applications | 502 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5395902
[patent_doc_number] => 20090315965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-24
[patent_title] => 'LED ARRAY MANUFACTURING METHOD, LED ARRAY AND LED PRINTER'
[patent_app_type] => utility
[patent_app_number] => 12/373626
[patent_app_country] => US
[patent_app_date] => 2007-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12152
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0315/20090315965.pdf
[firstpage_image] =>[orig_patent_app_number] => 12373626
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/373626 | LED ARRAY MANUFACTURING METHOD, LED ARRAY AND LED PRINTER | Oct 23, 2007 | Abandoned |
Array
(
[id] => 5327072
[patent_doc_number] => 20090107549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'PERCOLATING AMORPHOUS SILICON SOLAR CELL'
[patent_app_type] => utility
[patent_app_number] => 11/923406
[patent_app_country] => US
[patent_app_date] => 2007-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3355
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20090107549.pdf
[firstpage_image] =>[orig_patent_app_number] => 11923406
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/923406 | PERCOLATING AMORPHOUS SILICON SOLAR CELL | Oct 23, 2007 | Abandoned |
Array
(
[id] => 5282425
[patent_doc_number] => 20090096099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/874112
[patent_app_country] => US
[patent_app_date] => 2007-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5565
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20090096099.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874112
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874112 | Package substrate and method for fabricating the same | Oct 16, 2007 | Issued |
Array
(
[id] => 5282359
[patent_doc_number] => 20090096033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS'
[patent_app_type] => utility
[patent_app_number] => 11/873205
[patent_app_country] => US
[patent_app_date] => 2007-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4129
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
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[pdf_file] => publications/A1/0096/20090096033.pdf
[firstpage_image] =>[orig_patent_app_number] => 11873205
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873205 | Isolation trench with rounded corners for BiCMOS process | Oct 15, 2007 | Issued |
Array
(
[id] => 4731277
[patent_doc_number] => 20080048300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'Silicon epitaxial wafer and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/907572
[patent_app_country] => US
[patent_app_date] => 2007-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4000
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20080048300.pdf
[firstpage_image] =>[orig_patent_app_number] => 11907572
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907572 | Silicon epitaxial wafer and method for manufacturing the same | Oct 14, 2007 | Abandoned |
Array
(
[id] => 4909772
[patent_doc_number] => 20080020538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-24
[patent_title] => 'One Mask High Density Capacitor for Integrated Circuits'
[patent_app_type] => utility
[patent_app_number] => 11/862632
[patent_app_country] => US
[patent_app_date] => 2007-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1898
[patent_no_of_claims] => 11
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[pdf_file] => publications/A1/0020/20080020538.pdf
[firstpage_image] =>[orig_patent_app_number] => 11862632
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/862632 | One Mask High Density Capacitor for Integrated Circuits | Sep 26, 2007 | Abandoned |
Array
(
[id] => 6408833
[patent_doc_number] => 20100140586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-10
[patent_title] => 'QUANTUM DOTS HAVING COMPOSITION GRADIENT SHELL STRUCTURE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/442943
[patent_app_country] => US
[patent_app_date] => 2007-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4663
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
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[pdf_file] => publications/A1/0140/20100140586.pdf
[firstpage_image] =>[orig_patent_app_number] => 12442943
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/442943 | QUANTUM DOTS HAVING COMPOSITION GRADIENT SHELL STRUCTURE AND MANUFACTURING METHOD THEREOF | Sep 20, 2007 | Abandoned |
Array
(
[id] => 4876670
[patent_doc_number] => 20080150053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Image Sensor and Fabricating Method Thereof'
[patent_app_type] => utility
[patent_app_number] => 11/858306
[patent_app_country] => US
[patent_app_date] => 2007-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1638
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[pdf_file] => publications/A1/0150/20080150053.pdf
[firstpage_image] =>[orig_patent_app_number] => 11858306
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/858306 | Image sensor and fabricating method thereof | Sep 19, 2007 | Issued |
Array
(
[id] => 6247091
[patent_doc_number] => 20100025696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'Process for Producing a Silicon Carbide Substrate for Microelectric Applications'
[patent_app_type] => utility
[patent_app_number] => 12/442705
[patent_app_country] => US
[patent_app_date] => 2007-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1919
[patent_no_of_claims] => 18
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[pdf_file] => publications/A1/0025/20100025696.pdf
[firstpage_image] =>[orig_patent_app_number] => 12442705
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/442705 | Process for Producing a Silicon Carbide Substrate for Microelectric Applications | Sep 18, 2007 | Abandoned |
Array
(
[id] => 122648
[patent_doc_number] => 07704810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-27
[patent_title] => 'Manufacturing method of display device'
[patent_app_type] => utility
[patent_app_number] => 11/857481
[patent_app_country] => US
[patent_app_date] => 2007-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 40
[patent_no_of_words] => 18258
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/704/07704810.pdf
[firstpage_image] =>[orig_patent_app_number] => 11857481
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/857481 | Manufacturing method of display device | Sep 18, 2007 | Issued |
Array
(
[id] => 4768751
[patent_doc_number] => 20080054407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/896206
[patent_app_country] => US
[patent_app_date] => 2007-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1608
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[pdf_file] => publications/A1/0054/20080054407.pdf
[firstpage_image] =>[orig_patent_app_number] => 11896206
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/896206 | Semiconductor device and manufacturing method thereof | Aug 29, 2007 | Issued |
Array
(
[id] => 4949514
[patent_doc_number] => 20080305640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'METHOD FOR PREPARING TRENCH POWER TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 11/843971
[patent_app_country] => US
[patent_app_date] => 2007-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0305/20080305640.pdf
[firstpage_image] =>[orig_patent_app_number] => 11843971
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/843971 | METHOD FOR PREPARING TRENCH POWER TRANSISTORS | Aug 22, 2007 | Abandoned |
Array
(
[id] => 5334508
[patent_doc_number] => 20090050972
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-26
[patent_title] => 'Strained Semiconductor Device and Method of Making Same'
[patent_app_type] => utility
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Array
(
[id] => 74181
[patent_doc_number] => 07749907
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-06
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/841361
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Array
(
[id] => 5361108
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[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH'
[patent_app_type] => utility
[patent_app_number] => 11/831031
[patent_app_country] => US
[patent_app_date] => 2007-07-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/831031 | INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH | Jul 30, 2007 | Abandoned |
Array
(
[id] => 4669898
[patent_doc_number] => 20080044958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'Method of fabricating complementary metal-oxide semiconductor (CMOS) thin film transistor (TFT)'
[patent_app_type] => utility
[patent_app_number] => 11/878302
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/878302 | Method of fabricating complementary metal-oxide semiconductor (CMOS) thin film transistor (TFT) | Jul 22, 2007 | Issued |
Array
(
[id] => 4657678
[patent_doc_number] => 20080026539
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[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'Capacitance element manufacturing method and etching method'
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[patent_app_number] => 11/878172
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Array
(
[id] => 4909741
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[patent_title] => 'Method for manufacturing semiconductor integrated circuit device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826422 | Method for manufacturing semiconductor integrated circuit device | Jul 15, 2007 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/827715 | Process of forming and controlling rough interfaces | Jul 12, 2007 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/824212 | Forming vias using sacrificial material | Jun 28, 2007 | Issued |