Search

Daniel V. Venne

Examiner (ID: 394)

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
2006
Issued Applications
1406
Pending Applications
132
Abandoned Applications
502

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 326554 [patent_doc_number] => 07514325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Fin-FET having GAA structure and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/505936 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6304 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514325.pdf [firstpage_image] =>[orig_patent_app_number] => 11505936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/505936
Fin-FET having GAA structure and methods of fabricating the same Aug 17, 2006 Issued
Array ( [id] => 4564358 [patent_doc_number] => 07846776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods' [patent_app_type] => utility [patent_app_number] => 11/506372 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4420 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846776.pdf [firstpage_image] =>[orig_patent_app_number] => 11506372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/506372
Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods Aug 16, 2006 Issued
Array ( [id] => 5005125 [patent_doc_number] => 20070202695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/504585 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 5049 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20070202695.pdf [firstpage_image] =>[orig_patent_app_number] => 11504585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504585
Method for fabricating a semiconductor device Aug 15, 2006 Abandoned
Array ( [id] => 5154476 [patent_doc_number] => 20070037359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method of forming align key in well structure formation process and method of forming element isolation structure using the align key' [patent_app_type] => utility [patent_app_number] => 11/503782 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5990 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037359.pdf [firstpage_image] =>[orig_patent_app_number] => 11503782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/503782
Method of forming align key in well structure formation process and method of forming element isolation structure using the align key Aug 13, 2006 Abandoned
Array ( [id] => 4997594 [patent_doc_number] => 20070040228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Semiconductor device utilizing a metal gate material such as tungsten and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/502072 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2876 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040228.pdf [firstpage_image] =>[orig_patent_app_number] => 11502072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502072
Semiconductor device utilizing a metal gate material such as tungsten and method of manufacturing the same Aug 9, 2006 Issued
Array ( [id] => 4648797 [patent_doc_number] => 20080036052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE' [patent_app_type] => utility [patent_app_number] => 11/463505 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036052.pdf [firstpage_image] =>[orig_patent_app_number] => 11463505 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463505
Integrated circuit package system with supported stacked die Aug 8, 2006 Issued
Array ( [id] => 4688294 [patent_doc_number] => 20080032475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'MEMORY CELL SYSTEM WITH GRADIENT CHARGE ISOLATION' [patent_app_type] => utility [patent_app_number] => 11/462009 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032475.pdf [firstpage_image] =>[orig_patent_app_number] => 11462009 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462009
MEMORY CELL SYSTEM WITH GRADIENT CHARGE ISOLATION Aug 1, 2006 Abandoned
Array ( [id] => 359678 [patent_doc_number] => 07485557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for fabricating semiconductor device having flask type recess gate' [patent_app_type] => utility [patent_app_number] => 11/496428 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485557.pdf [firstpage_image] =>[orig_patent_app_number] => 11496428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/496428
Method for fabricating semiconductor device having flask type recess gate Jul 31, 2006 Issued
Array ( [id] => 4657656 [patent_doc_number] => 20080026517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'METHOD FOR FORMING A STRESSOR LAYER' [patent_app_type] => utility [patent_app_number] => 11/460742 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026517.pdf [firstpage_image] =>[orig_patent_app_number] => 11460742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460742
METHOD FOR FORMING A STRESSOR LAYER Jul 27, 2006 Abandoned
Array ( [id] => 5204668 [patent_doc_number] => 20070026149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Semiconductor manufacturing apparatus and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/494735 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026149.pdf [firstpage_image] =>[orig_patent_app_number] => 11494735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/494735
Semiconductor manufacturing apparatus and method of manufacturing semiconductor device Jul 27, 2006 Abandoned
Array ( [id] => 5107205 [patent_doc_number] => 20070066083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 11/494451 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12144 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20070066083.pdf [firstpage_image] =>[orig_patent_app_number] => 11494451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/494451
Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same Jul 27, 2006 Issued
Array ( [id] => 5038144 [patent_doc_number] => 20070090426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Ferroelectric capacitor' [patent_app_type] => utility [patent_app_number] => 11/493525 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5157 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090426.pdf [firstpage_image] =>[orig_patent_app_number] => 11493525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493525
Ferroelectric capacitor Jul 26, 2006 Abandoned
Array ( [id] => 4654945 [patent_doc_number] => 20080023805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Array-Processed Stacked Semiconductor Packages' [patent_app_type] => utility [patent_app_number] => 11/460101 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7259 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023805.pdf [firstpage_image] =>[orig_patent_app_number] => 11460101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460101
Array-Processed Stacked Semiconductor Packages Jul 25, 2006 Abandoned
Array ( [id] => 260355 [patent_doc_number] => 07573082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'CMOS image sensor and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/491236 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4163 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/573/07573082.pdf [firstpage_image] =>[orig_patent_app_number] => 11491236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491236
CMOS image sensor and method of fabricating the same Jul 23, 2006 Issued
Array ( [id] => 101955 [patent_doc_number] => 07727816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Integrated circuit package system with offset stacked die' [patent_app_type] => utility [patent_app_number] => 11/459305 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 3922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/727/07727816.pdf [firstpage_image] =>[orig_patent_app_number] => 11459305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459305
Integrated circuit package system with offset stacked die Jul 20, 2006 Issued
Array ( [id] => 4608684 [patent_doc_number] => 07993939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Integrated circuit package system with laminate base' [patent_app_type] => utility [patent_app_number] => 11/459325 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3881 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/993/07993939.pdf [firstpage_image] =>[orig_patent_app_number] => 11459325 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459325
Integrated circuit package system with laminate base Jul 20, 2006 Issued
Array ( [id] => 5040722 [patent_doc_number] => 20070093004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Method of manufacturing thin film transistor including ZnO thin layer' [patent_app_type] => utility [patent_app_number] => 11/488895 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3691 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20070093004.pdf [firstpage_image] =>[orig_patent_app_number] => 11488895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/488895
Method of manufacturing thin film transistor including ZnO thin layer Jul 18, 2006 Abandoned
Array ( [id] => 5242404 [patent_doc_number] => 20070020899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Forming method for film pattern, device, electro-optical apparatus, electronic apparatus, and manufacturing method for active matrix substrate' [patent_app_type] => utility [patent_app_number] => 11/488856 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18098 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020899.pdf [firstpage_image] =>[orig_patent_app_number] => 11488856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/488856
Forming method for film pattern, device, electro-optical apparatus, electronic apparatus, and manufacturing method for active matrix substrate Jul 17, 2006 Issued
Array ( [id] => 8896650 [patent_doc_number] => 08476171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Heat treatment method of ZnTe single crystal substrate and ZnTe single crystal substrate' [patent_app_type] => utility [patent_app_number] => 11/988755 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3791 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11988755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/988755
Heat treatment method of ZnTe single crystal substrate and ZnTe single crystal substrate Jul 17, 2006 Issued
Array ( [id] => 74104 [patent_doc_number] => 07749858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Process for producing an MOS transistor and corresponding integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/487706 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2514 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/749/07749858.pdf [firstpage_image] =>[orig_patent_app_number] => 11487706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/487706
Process for producing an MOS transistor and corresponding integrated circuit Jul 16, 2006 Issued
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