
Daniel V. Venne
Examiner (ID: 394)
| Most Active Art Unit | 3617 |
| Art Unit(s) | 3617, 3615 |
| Total Applications | 2006 |
| Issued Applications | 1406 |
| Pending Applications | 132 |
| Abandoned Applications | 502 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 246941
[patent_doc_number] => 07585693
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-08
[patent_title] => 'Method of forming a microelectronic package using control of die and substrate differential expansions and microelectronic package formed according to the method'
[patent_app_type] => utility
[patent_app_number] => 11/395102
[patent_app_country] => US
[patent_app_date] => 2006-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5161
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/585/07585693.pdf
[firstpage_image] =>[orig_patent_app_number] => 11395102
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/395102 | Method of forming a microelectronic package using control of die and substrate differential expansions and microelectronic package formed according to the method | Mar 30, 2006 | Issued |
Array
(
[id] => 7691985
[patent_doc_number] => 20070232048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Damascene interconnection having a SiCOH low k layer'
[patent_app_type] => utility
[patent_app_number] => 11/395962
[patent_app_country] => US
[patent_app_date] => 2006-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3573
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20070232048.pdf
[firstpage_image] =>[orig_patent_app_number] => 11395962
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/395962 | Damascene interconnection having a SiCOH low k layer | Mar 30, 2006 | Abandoned |
Array
(
[id] => 170605
[patent_doc_number] => 07662718
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-16
[patent_title] => 'Trim process for critical dimension control for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/372825
[patent_app_country] => US
[patent_app_date] => 2006-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 8131
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/662/07662718.pdf
[firstpage_image] =>[orig_patent_app_number] => 11372825
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/372825 | Trim process for critical dimension control for integrated circuits | Mar 8, 2006 | Issued |
Array
(
[id] => 5157541
[patent_doc_number] => 20070170585
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-26
[patent_title] => 'Composite integrated device and methods for forming thereof'
[patent_app_type] => utility
[patent_app_number] => 11/368720
[patent_app_country] => US
[patent_app_date] => 2006-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2950
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20070170585.pdf
[firstpage_image] =>[orig_patent_app_number] => 11368720
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/368720 | Composite integrated device and methods for forming thereof | Mar 5, 2006 | Issued |
Array
(
[id] => 5159731
[patent_doc_number] => 20070172775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-26
[patent_title] => 'Method of forming an organic semiconductor pattern and method of manufacturing an organic thin film transistor using the same'
[patent_app_type] => utility
[patent_app_number] => 11/336028
[patent_app_country] => US
[patent_app_date] => 2006-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6824
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20070172775.pdf
[firstpage_image] =>[orig_patent_app_number] => 11336028
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/336028 | Method of forming an organic semiconductor pattern and method of manufacturing an organic thin film transistor using the same | Jan 19, 2006 | Issued |
Array
(
[id] => 5700258
[patent_doc_number] => 20060216943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Method for forming metal line'
[patent_app_type] => utility
[patent_app_number] => 11/322002
[patent_app_country] => US
[patent_app_date] => 2005-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1375
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20060216943.pdf
[firstpage_image] =>[orig_patent_app_number] => 11322002
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/322002 | Method for forming metal line | Dec 29, 2005 | Abandoned |
Array
(
[id] => 5645925
[patent_doc_number] => 20060131657
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'Semiconductor integrated circuit device and method for the same'
[patent_app_type] => utility
[patent_app_number] => 11/296705
[patent_app_country] => US
[patent_app_date] => 2005-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5765
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20060131657.pdf
[firstpage_image] =>[orig_patent_app_number] => 11296705
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/296705 | Semiconductor integrated circuit device and method for the same | Dec 7, 2005 | Abandoned |
Array
(
[id] => 5236630
[patent_doc_number] => 20070128787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Method of forming low resistance void-free contacts'
[patent_app_type] => utility
[patent_app_number] => 11/296022
[patent_app_country] => US
[patent_app_date] => 2005-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5290
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20070128787.pdf
[firstpage_image] =>[orig_patent_app_number] => 11296022
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/296022 | Method of forming low resistance void-free contacts | Dec 5, 2005 | Issued |
Array
(
[id] => 5079818
[patent_doc_number] => 20070123042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-31
[patent_title] => 'METHODS TO FORM HETEROGENEOUS SILICIDES/GERMANIDES IN CMOS TECHNOLOGY'
[patent_app_type] => utility
[patent_app_number] => 11/164511
[patent_app_country] => US
[patent_app_date] => 2005-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4730
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0123/20070123042.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164511
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164511 | METHODS TO FORM HETEROGENEOUS SILICIDES/GERMANIDES IN CMOS TECHNOLOGY | Nov 27, 2005 | Abandoned |
Array
(
[id] => 5296653
[patent_doc_number] => 20090011579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-08
[patent_title] => 'Quantum Dot Array And Production Method Therefor, And Dot Array Element And Production Method Therefor'
[patent_app_type] => utility
[patent_app_number] => 11/791445
[patent_app_country] => US
[patent_app_date] => 2005-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 10186
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20090011579.pdf
[firstpage_image] =>[orig_patent_app_number] => 11791445
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/791445 | Quantum dot array and production method therefor, and dot array element and production method therefor | Nov 23, 2005 | Issued |
Array
(
[id] => 5107081
[patent_doc_number] => 20070065959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Method for manufacturing light-emitting diode'
[patent_app_type] => utility
[patent_app_number] => 11/273382
[patent_app_country] => US
[patent_app_date] => 2005-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2555
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20070065959.pdf
[firstpage_image] =>[orig_patent_app_number] => 11273382
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/273382 | Method for manufacturing light-emitting diode | Nov 11, 2005 | Abandoned |
Array
(
[id] => 307304
[patent_doc_number] => 07531370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-12
[patent_title] => 'Light-emitting diode and its manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/256001
[patent_app_country] => US
[patent_app_date] => 2005-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 6884
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/531/07531370.pdf
[firstpage_image] =>[orig_patent_app_number] => 11256001
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/256001 | Light-emitting diode and its manufacturing method | Oct 23, 2005 | Issued |
Array
(
[id] => 907008
[patent_doc_number] => 07332370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-19
[patent_title] => 'Method of manufacturing a phase change RAM device utilizing reduced phase change current'
[patent_app_type] => utility
[patent_app_number] => 11/254472
[patent_app_country] => US
[patent_app_date] => 2005-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2834
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/332/07332370.pdf
[firstpage_image] =>[orig_patent_app_number] => 11254472
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/254472 | Method of manufacturing a phase change RAM device utilizing reduced phase change current | Oct 19, 2005 | Issued |
Array
(
[id] => 369845
[patent_doc_number] => 07476618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Selective formation of metal layers in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/254071
[patent_app_country] => US
[patent_app_date] => 2005-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9900
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/476/07476618.pdf
[firstpage_image] =>[orig_patent_app_number] => 11254071
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/254071 | Selective formation of metal layers in an integrated circuit | Oct 17, 2005 | Issued |
Array
(
[id] => 5796503
[patent_doc_number] => 20060033180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers and method of making'
[patent_app_type] => utility
[patent_app_number] => 11/249212
[patent_app_country] => US
[patent_app_date] => 2005-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6538
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20060033180.pdf
[firstpage_image] =>[orig_patent_app_number] => 11249212
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/249212 | Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers and method of making | Oct 12, 2005 | Abandoned |
Array
(
[id] => 8533302
[patent_doc_number] => 08309456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-13
[patent_title] => 'Method and system for metal barrier and seed integration'
[patent_app_type] => utility
[patent_app_number] => 11/249141
[patent_app_country] => US
[patent_app_date] => 2005-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 5167
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 259
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11249141
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/249141 | Method and system for metal barrier and seed integration | Oct 10, 2005 | Issued |
Array
(
[id] => 5614039
[patent_doc_number] => 20060115967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'Methods of manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/246791
[patent_app_country] => US
[patent_app_date] => 2005-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5089
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20060115967.pdf
[firstpage_image] =>[orig_patent_app_number] => 11246791
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/246791 | Methods of manufacturing a semiconductor device | Oct 6, 2005 | Abandoned |
Array
(
[id] => 5136122
[patent_doc_number] => 20070077751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-05
[patent_title] => 'METHOD OF RESTORING LOW-K MATERIAL OR POROUS LOW-K LAYER'
[patent_app_type] => utility
[patent_app_number] => 11/163051
[patent_app_country] => US
[patent_app_date] => 2005-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2066
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20070077751.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163051
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163051 | METHOD OF RESTORING LOW-K MATERIAL OR POROUS LOW-K LAYER | Oct 2, 2005 | Abandoned |
Array
(
[id] => 5136109
[patent_doc_number] => 20070077738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-05
[patent_title] => 'Fabrication of small scale matched bi-polar TVS devices having reduced parasitic losses'
[patent_app_type] => utility
[patent_app_number] => 11/243161
[patent_app_country] => US
[patent_app_date] => 2005-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2975
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20070077738.pdf
[firstpage_image] =>[orig_patent_app_number] => 11243161
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/243161 | Fabrication of small scale matched bi-polar TVS devices having reduced parasitic losses | Oct 2, 2005 | Abandoned |
Array
(
[id] => 5637595
[patent_doc_number] => 20060068568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Silicon epitaxial wafer and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/235091
[patent_app_country] => US
[patent_app_date] => 2005-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4000
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20060068568.pdf
[firstpage_image] =>[orig_patent_app_number] => 11235091
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/235091 | Silicon epitaxial wafer and method for manufacturing the same | Sep 26, 2005 | Issued |