Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6746628 [patent_doc_number] => 20030023811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method for managing logical volume in order to support dynamic online resizing and software raid' [patent_app_type] => new [patent_app_number] => 10/005604 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6564 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023811.pdf [firstpage_image] =>[orig_patent_app_number] => 10005604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005604
Method for managing logical volume in order to support dynamic online resizing and software raid and to minimize metadata and computer readable medium storing the same Dec 6, 2001 Issued
Array ( [id] => 7623852 [patent_doc_number] => 06725325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function' [patent_app_type] => B2 [patent_app_number] => 10/005361 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7471 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725325.pdf [firstpage_image] =>[orig_patent_app_number] => 10005361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005361
Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function Dec 6, 2001 Issued
Array ( [id] => 1161622 [patent_doc_number] => 06775759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Sequential nibble burst ordering for data' [patent_app_type] => B2 [patent_app_number] => 10/008710 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3893 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775759.pdf [firstpage_image] =>[orig_patent_app_number] => 10008710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008710
Sequential nibble burst ordering for data Dec 6, 2001 Issued
Array ( [id] => 5971428 [patent_doc_number] => 20020091899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Concurrent access scheme for exclusive mode cache' [patent_app_type] => new [patent_app_number] => 10/013302 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3785 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091899.pdf [firstpage_image] =>[orig_patent_app_number] => 10013302 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013302
Concurrent access scheme for exclusive mode cache Dec 6, 2001 Issued
Array ( [id] => 7623854 [patent_doc_number] => 06725323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Apparatus and method for updating flash ROM in an electronic apparatus having a plurality of boards' [patent_app_type] => B2 [patent_app_number] => 10/003253 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5612 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725323.pdf [firstpage_image] =>[orig_patent_app_number] => 10003253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003253
Apparatus and method for updating flash ROM in an electronic apparatus having a plurality of boards Dec 5, 2001 Issued
Array ( [id] => 1149551 [patent_doc_number] => 06782450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'File mode RAID subsystem' [patent_app_type] => B2 [patent_app_number] => 10/011224 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/782/06782450.pdf [firstpage_image] =>[orig_patent_app_number] => 10011224 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011224
File mode RAID subsystem Dec 5, 2001 Issued
Array ( [id] => 6698164 [patent_doc_number] => 20030110358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Efficient automatic means for ensuring data cache coherency' [patent_app_type] => new [patent_app_number] => 10/010224 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3980 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110358.pdf [firstpage_image] =>[orig_patent_app_number] => 10010224 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010224
Cache synchronization method, system and apparatus for a distributed application and an object located in a client cache Dec 5, 2001 Issued
Array ( [id] => 6181356 [patent_doc_number] => 20020156986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Storage medium, a data obtaining apparatus, a data holding apparatus, a data obtaining method, and a data holding method' [patent_app_type] => new [patent_app_number] => 09/980782 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10366 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156986.pdf [firstpage_image] =>[orig_patent_app_number] => 09980782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/980782
Apparatus and method for storing data in a storage medium, while saving storage areas which are used for holding a data path name and become necessary in response to the storing of data Dec 5, 2001 Issued
Array ( [id] => 5830453 [patent_doc_number] => 20020069320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Disk storage accessing system' [patent_app_type] => new [patent_app_number] => 10/003095 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2648 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069320.pdf [firstpage_image] =>[orig_patent_app_number] => 10003095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003095
Disk storage accessing system and method for changing access path to storage devices Dec 5, 2001 Issued
Array ( [id] => 6685024 [patent_doc_number] => 20030120888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Address range checking circuit and method of operation' [patent_app_type] => new [patent_app_number] => 10/008726 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5818 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120888.pdf [firstpage_image] =>[orig_patent_app_number] => 10008726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008726
Address range checking circuit and method of operation Dec 4, 2001 Issued
Array ( [id] => 6655431 [patent_doc_number] => 20030105926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Variable size prefetch cache' [patent_app_type] => new [patent_app_number] => 10/008449 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4018 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20030105926.pdf [firstpage_image] =>[orig_patent_app_number] => 10008449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008449
Variable size prefetch cache Dec 2, 2001 Abandoned
Array ( [id] => 6388948 [patent_doc_number] => 20020120825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Automatic detection and correction of relatively rearranged and/or inverted data and address signals to shared memory' [patent_app_type] => new [patent_app_number] => 09/998331 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120825.pdf [firstpage_image] =>[orig_patent_app_number] => 09998331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998331
Automatic detection and correction of relatively rearranged and/or inverted data and address signals to shared memory Dec 2, 2001 Issued
Array ( [id] => 6066293 [patent_doc_number] => 20020032830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers' [patent_app_type] => new [patent_app_number] => 09/989109 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8681 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032830.pdf [firstpage_image] =>[orig_patent_app_number] => 09989109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989109
Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers Nov 20, 2001 Issued
Array ( [id] => 6001635 [patent_doc_number] => 20020029324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Data receiver that performs synchronous data transfer with reference to memory module' [patent_app_type] => new [patent_app_number] => 09/983600 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11400 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20020029324.pdf [firstpage_image] =>[orig_patent_app_number] => 09983600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983600
Data receiver that performs synchronous data transfer with reference to memory module Oct 24, 2001 Issued
Array ( [id] => 6211559 [patent_doc_number] => 20020073291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Selective transfer of data between storage devices through utilization of dynamic memory allocation' [patent_app_type] => new [patent_app_number] => 09/923854 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6014 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073291.pdf [firstpage_image] =>[orig_patent_app_number] => 09923854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923854
System for selectively transferring application data between storage devices in a computer system utilizing dynamic memory allocation Aug 6, 2001 Issued
Array ( [id] => 6988678 [patent_doc_number] => 20010037429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Balanced switching method and circuit' [patent_app_type] => new [patent_app_number] => 09/891567 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4685 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037429.pdf [firstpage_image] =>[orig_patent_app_number] => 09891567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891567
Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times Jun 24, 2001 Issued
Array ( [id] => 1225563 [patent_doc_number] => 06704840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Computer system and method of computer initialization with caching of option BIOS' [patent_app_type] => B2 [patent_app_number] => 09/883401 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3343 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704840.pdf [firstpage_image] =>[orig_patent_app_number] => 09883401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/883401
Computer system and method of computer initialization with caching of option BIOS Jun 18, 2001 Issued
Array ( [id] => 1155186 [patent_doc_number] => 06779094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Apparatus and method for instant copy of data by writing new data to an additional physical storage area' [patent_app_type] => B2 [patent_app_number] => 09/884687 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 14950 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779094.pdf [firstpage_image] =>[orig_patent_app_number] => 09884687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884687
Apparatus and method for instant copy of data by writing new data to an additional physical storage area Jun 18, 2001 Issued
Array ( [id] => 6881006 [patent_doc_number] => 20010032294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Disk array device with selectable method for generating redundant data' [patent_app_type] => new [patent_app_number] => 09/883179 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8254 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032294.pdf [firstpage_image] =>[orig_patent_app_number] => 09883179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/883179
Disk array device with selectable method for generating redundant data Jun 18, 2001 Issued
Array ( [id] => 1271779 [patent_doc_number] => 06662261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Data processing arrangement and method for connecting storage elements and groups selectively to processing circuits' [patent_app_type] => B2 [patent_app_number] => 09/884220 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4484 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662261.pdf [firstpage_image] =>[orig_patent_app_number] => 09884220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884220
Data processing arrangement and method for connecting storage elements and groups selectively to processing circuits Jun 18, 2001 Issued
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