Danielle Jackson

Array ( [id] => 1271779 [patent_doc_number] => 06662261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Data processing arrangement and method for connecting storage elements and groups selectively to processing circuits' [patent_app_type] => B2 [patent_app_number] => 09/884220 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4484 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662261.pdf [firstpage_image] =>[orig_patent_app_number] => 09884220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1356884 [patent_doc_number] => 06591330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'System and method for flexible flash file' [patent_app_type] => B2 [patent_app_number] => 09/882056 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5711 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591330.pdf [firstpage_image] =>[orig_patent_app_number] => 09882056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6531863 [patent_doc_number] => 20020026562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Two-way cache system and method of operation for interfacing with a peripheral device' [patent_app_type] => new [patent_app_number] => 09/881861 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4278 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026562.pdf [firstpage_image] =>[orig_patent_app_number] => 09881861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629987 [patent_doc_number] => 06636952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Systems and methods for processing packet streams in a network device' [patent_app_type] => B1 [patent_app_number] => 09/880873 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 8020 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636952.pdf [firstpage_image] =>[orig_patent_app_number] => 09880873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1258429 [patent_doc_number] => 06671791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Processor including a translation unit for selectively translating virtual addresses of different sizes using a plurality of paging tables and mapping mechanisms' [patent_app_type] => B1 [patent_app_number] => 09/881910 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 19044 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671791.pdf [firstpage_image] =>[orig_patent_app_number] => 09881910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7001781 [patent_doc_number] => 20010054135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Memory control technique' [patent_app_type] => new [patent_app_number] => 09/880938 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3366 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054135.pdf [firstpage_image] =>[orig_patent_app_number] => 09880938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1258369 [patent_doc_number] => 06671777 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Data storage system and method for managing critical data in an N-way mirrored storage device using first and second sequence numbers' [patent_app_type] => B1 [patent_app_number] => 09/883141 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3881 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671777.pdf [firstpage_image] =>[orig_patent_app_number] => 09883141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415540 [patent_doc_number] => 06549974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Semiconductor storage apparatus including a controller for sending first and second write commands to different nonvolatile memories in a parallel or time overlapped manner' [patent_app_type] => B2 [patent_app_number] => 09/879960 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6461 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549974.pdf [firstpage_image] =>[orig_patent_app_number] => 09879960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169794 [patent_doc_number] => 06766408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Semiconductor integrated circuit and method for writing into non-volatile memory using a program received by external communication' [patent_app_type] => B2 [patent_app_number] => 09/881193 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4450 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766408.pdf [firstpage_image] =>[orig_patent_app_number] => 09881193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6554564 [patent_doc_number] => 20020194444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'System and method for managing out-of-order memory access requests via an age-shifted index' [patent_app_type] => new [patent_app_number] => 09/880994 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4971 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194444.pdf [firstpage_image] =>[orig_patent_app_number] => 09880994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1221724 [patent_doc_number] => 06708258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Computer system for eliminating memory read-modify-write operations during packet transfers' [patent_app_type] => B1 [patent_app_number] => 09/881280 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5346 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708258.pdf [firstpage_image] =>[orig_patent_app_number] => 09881280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6554484 [patent_doc_number] => 20020194437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Methodology to stress and test LPAR isolation features' [patent_app_type] => new [patent_app_number] => 09/881920 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4694 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194437.pdf [firstpage_image] =>[orig_patent_app_number] => 09881920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311259 [patent_doc_number] => 06625697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Cache-storage device with a buffer storing prefetch data' [patent_app_type] => B1 [patent_app_number] => 09/831900 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2351 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625697.pdf [firstpage_image] =>[orig_patent_app_number] => 09831900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1234278 [patent_doc_number] => 06697922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Apparatus for transferring data from a memory unit to a digitally switched potentiometer using a microcontroller' [patent_app_type] => B2 [patent_app_number] => 09/880664 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2117 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697922.pdf [firstpage_image] =>[orig_patent_app_number] => 09880664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6899292 [patent_doc_number] => 20010047457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Digital data processor with improved paging' [patent_app_type] => new [patent_app_number] => 09/854375 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13577 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047457.pdf [firstpage_image] =>[orig_patent_app_number] => 09854375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1165711 [patent_doc_number] => 06772277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method of writing to a memory array using clear enable and column clear signals' [patent_app_type] => B2 [patent_app_number] => 09/845387 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2097 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772277.pdf [firstpage_image] =>[orig_patent_app_number] => 09845387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183495 [patent_doc_number] => 06751700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Date processor and storage system including a set associative cache with memory aliasing' [patent_app_type] => B2 [patent_app_number] => 09/822244 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2912 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751700.pdf [firstpage_image] =>[orig_patent_app_number] => 09822244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5910544 [patent_doc_number] => 20020144080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Descriptor table storing segment descriptors of varying size' [patent_app_type] => new [patent_app_number] => 09/824995 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13928 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144080.pdf [firstpage_image] =>[orig_patent_app_number] => 09824995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5890306 [patent_doc_number] => 20020013864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Queuing architecture including a plurality of queues and assocated method for controlling admission for disk access requests for video content' [patent_app_type] => new [patent_app_number] => 09/801021 [patent_app_country] => US [patent_app_date] => 2001-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9383 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013864.pdf [firstpage_image] =>[orig_patent_app_number] => 09801021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423695 [patent_doc_number] => 06539474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'System and method for selectively executing different boot routines depending on whether an error is detected' [patent_app_type] => B2 [patent_app_number] => 09/782854 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5304 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539474.pdf [firstpage_image] =>[orig_patent_app_number] => 09782854 [rel_patent_id] =>[rel_patent_doc_number] =>)