Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1105977 [patent_doc_number] => 06816888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Communication process and system with service access points and groups of references where participant addresses are used to access a particular reference' [patent_app_type] => B2 [patent_app_number] => 09/776716 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3062 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816888.pdf [firstpage_image] =>[orig_patent_app_number] => 09776716 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776716
Communication process and system with service access points and groups of references where participant addresses are used to access a particular reference Feb 5, 2001 Issued
Array ( [id] => 7638628 [patent_doc_number] => 06397293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface' [patent_app_type] => B2 [patent_app_number] => 09/767305 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5479 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397293.pdf [firstpage_image] =>[orig_patent_app_number] => 09767305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767305
Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface Jan 18, 2001 Issued
Array ( [id] => 6875722 [patent_doc_number] => 20010000816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Volatile lock architecture for individual block locking on flash memory' [patent_app_type] => new-utility [patent_app_number] => 09/748826 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000816.pdf [firstpage_image] =>[orig_patent_app_number] => 09748826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748826
Computing system with volatile lock architecture for individual block locking on flash memory Dec 25, 2000 Issued
Array ( [id] => 1456705 [patent_doc_number] => 06457092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Semiconductor disk storage apparatus including a plurality of flash memories and a buffer memory to continuously write data responsive to first and second write commands' [patent_app_type] => B1 [patent_app_number] => 09/706843 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6415 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 507 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457092.pdf [firstpage_image] =>[orig_patent_app_number] => 09706843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706843
Semiconductor disk storage apparatus including a plurality of flash memories and a buffer memory to continuously write data responsive to first and second write commands Nov 6, 2000 Issued
09/705114 APPARATUS AND METHOD FOR CACHING DATA AT NETWORK SITES UTLIZING DIFFERENT CACHE MANAGEMENT ALGORITHMS Nov 1, 2000 Abandoned
Array ( [id] => 1431087 [patent_doc_number] => 06507900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Semiconductor memory device including plural blocks with selecting and sensing or reading operations in different blocks carried out in parallel' [patent_app_type] => B1 [patent_app_number] => 09/698242 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 78 [patent_no_of_words] => 13567 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507900.pdf [firstpage_image] =>[orig_patent_app_number] => 09698242 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/698242
Semiconductor memory device including plural blocks with selecting and sensing or reading operations in different blocks carried out in parallel Oct 29, 2000 Issued
Array ( [id] => 1165676 [patent_doc_number] => 06772274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Flash memory system and method implementing LBA to PBA correlation within flash memory array' [patent_app_type] => B1 [patent_app_number] => 09/660838 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 13962 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772274.pdf [firstpage_image] =>[orig_patent_app_number] => 09660838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660838
Flash memory system and method implementing LBA to PBA correlation within flash memory array Sep 12, 2000 Issued
Array ( [id] => 1218206 [patent_doc_number] => 06711664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method and system for decoding a row address to assert multiple adjacent rows in a memory structure' [patent_app_type] => B1 [patent_app_number] => 09/660721 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2964 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711664.pdf [firstpage_image] =>[orig_patent_app_number] => 09660721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660721
Method and system for decoding a row address to assert multiple adjacent rows in a memory structure Sep 12, 2000 Issued
Array ( [id] => 1444072 [patent_doc_number] => 06496900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Disk array system, controller, and method for verifying command data written to disk drives' [patent_app_type] => B1 [patent_app_number] => 09/659974 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2589 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496900.pdf [firstpage_image] =>[orig_patent_app_number] => 09659974 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659974
Disk array system, controller, and method for verifying command data written to disk drives Sep 11, 2000 Issued
Array ( [id] => 7633093 [patent_doc_number] => 06658527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Recording and/or reproduction apparatus and data communication system with display of main and auxiliary data recorded capacity information' [patent_app_type] => B1 [patent_app_number] => 09/660304 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 37 [patent_no_of_words] => 30382 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658527.pdf [firstpage_image] =>[orig_patent_app_number] => 09660304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660304
Recording and/or reproduction apparatus and data communication system with display of main and auxiliary data recorded capacity information Sep 11, 2000 Issued
Array ( [id] => 1234237 [patent_doc_number] => 06697909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory' [patent_app_type] => B1 [patent_app_number] => 09/660431 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697909.pdf [firstpage_image] =>[orig_patent_app_number] => 09660431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660431
Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory Sep 11, 2000 Issued
Array ( [id] => 1406534 [patent_doc_number] => 06560671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses' [patent_app_type] => B1 [patent_app_number] => 09/659237 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2065 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560671.pdf [firstpage_image] =>[orig_patent_app_number] => 09659237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659237
Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses Sep 10, 2000 Issued
Array ( [id] => 1347674 [patent_doc_number] => 06598112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and apparatus for executing a program using primary, secondary and tertiary memories' [patent_app_type] => B1 [patent_app_number] => 09/659259 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12754 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598112.pdf [firstpage_image] =>[orig_patent_app_number] => 09659259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659259
Method and apparatus for executing a program using primary, secondary and tertiary memories Sep 10, 2000 Issued
Array ( [id] => 1291953 [patent_doc_number] => 06643761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations' [patent_app_type] => B1 [patent_app_number] => 09/658022 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2221 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643761.pdf [firstpage_image] =>[orig_patent_app_number] => 09658022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658022
Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations Sep 7, 2000 Issued
Array ( [id] => 1418664 [patent_doc_number] => 06546456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and apparatus for operating vehicle mounted disk drive storage device' [patent_app_type] => B1 [patent_app_number] => 09/657879 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8353 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546456.pdf [firstpage_image] =>[orig_patent_app_number] => 09657879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657879
Method and apparatus for operating vehicle mounted disk drive storage device Sep 7, 2000 Issued
Array ( [id] => 1353099 [patent_doc_number] => 06594727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Entertainment system which includes an information processing unit capable of communicating with detachable portable storage device even after insertion of a different portable storage device' [patent_app_type] => B1 [patent_app_number] => 09/658176 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3930 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594727.pdf [firstpage_image] =>[orig_patent_app_number] => 09658176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658176
Entertainment system which includes an information processing unit capable of communicating with detachable portable storage device even after insertion of a different portable storage device Sep 7, 2000 Issued
Array ( [id] => 1169685 [patent_doc_number] => 06763437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Control system, storage device and method for controlling access to a shared memory using a bus control or handshaking protocol' [patent_app_type] => B1 [patent_app_number] => 09/656529 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9444 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763437.pdf [firstpage_image] =>[orig_patent_app_number] => 09656529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656529
Control system, storage device and method for controlling access to a shared memory using a bus control or handshaking protocol Sep 6, 2000 Issued
Array ( [id] => 1165851 [patent_doc_number] => 06772288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Extended cache memory system and method for caching data including changing a state field value in an extent record' [patent_app_type] => B1 [patent_app_number] => 09/655952 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4664 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772288.pdf [firstpage_image] =>[orig_patent_app_number] => 09655952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655952
Extended cache memory system and method for caching data including changing a state field value in an extent record Sep 5, 2000 Issued
Array ( [id] => 1425229 [patent_doc_number] => 06535959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Circuit and method for reducing power consumption in an instruction cache' [patent_app_type] => B1 [patent_app_number] => 09/654811 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8326 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535959.pdf [firstpage_image] =>[orig_patent_app_number] => 09654811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654811
Circuit and method for reducing power consumption in an instruction cache Sep 4, 2000 Issued
Array ( [id] => 1218174 [patent_doc_number] => 06711651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching' [patent_app_type] => B1 [patent_app_number] => 09/655642 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5106 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711651.pdf [firstpage_image] =>[orig_patent_app_number] => 09655642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655642
Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching Sep 4, 2000 Issued
Menu