Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1400883 [patent_doc_number] => 06564287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Semiconductor memory device having a fixed CAS latency and/or burst length' [patent_app_type] => B1 [patent_app_number] => 09/655643 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5946 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564287.pdf [firstpage_image] =>[orig_patent_app_number] => 09655643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655643
Semiconductor memory device having a fixed CAS latency and/or burst length Sep 4, 2000 Issued
Array ( [id] => 1196934 [patent_doc_number] => 06732227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Network translation circuit and method using a segmentable content addressable memory' [patent_app_type] => B1 [patent_app_number] => 09/655019 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7510 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732227.pdf [firstpage_image] =>[orig_patent_app_number] => 09655019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655019
Network translation circuit and method using a segmentable content addressable memory Sep 4, 2000 Issued
Array ( [id] => 1411437 [patent_doc_number] => 06553453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Variable width content addressable memory device for searching variable width data' [patent_app_type] => B1 [patent_app_number] => 09/654316 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7647 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553453.pdf [firstpage_image] =>[orig_patent_app_number] => 09654316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654316
Variable width content addressable memory device for searching variable width data Aug 31, 2000 Issued
Array ( [id] => 1365327 [patent_doc_number] => 06581142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Computer program product and method for partial paging and eviction of microprocessor instructions in an embedded computer' [patent_app_type] => B1 [patent_app_number] => 09/653673 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2911 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581142.pdf [firstpage_image] =>[orig_patent_app_number] => 09653673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653673
Computer program product and method for partial paging and eviction of microprocessor instructions in an embedded computer Aug 31, 2000 Issued
Array ( [id] => 1284515 [patent_doc_number] => 06651140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Caching pattern and method for caching in an object-oriented programming environment' [patent_app_type] => B1 [patent_app_number] => 09/654184 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4108 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651140.pdf [firstpage_image] =>[orig_patent_app_number] => 09654184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654184
Caching pattern and method for caching in an object-oriented programming environment Aug 31, 2000 Issued
Array ( [id] => 1401183 [patent_doc_number] => 06564304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching' [patent_app_type] => B1 [patent_app_number] => 09/653763 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3823 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564304.pdf [firstpage_image] =>[orig_patent_app_number] => 09653763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653763
Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching Aug 31, 2000 Issued
Array ( [id] => 1604475 [patent_doc_number] => 06434661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Synchronous semiconductor memory including register for storing data input and output mode information' [patent_app_type] => B1 [patent_app_number] => 09/640518 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 93 [patent_figures_cnt] => 117 [patent_no_of_words] => 45531 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434661.pdf [firstpage_image] =>[orig_patent_app_number] => 09640518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640518
Synchronous semiconductor memory including register for storing data input and output mode information Aug 16, 2000 Issued
Array ( [id] => 1431896 [patent_doc_number] => 06516395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes' [patent_app_type] => B1 [patent_app_number] => 09/626615 [patent_app_country] => US [patent_app_date] => 2000-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9663 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516395.pdf [firstpage_image] =>[orig_patent_app_number] => 09626615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626615
System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes Jul 26, 2000 Issued
Array ( [id] => 7634987 [patent_doc_number] => 06381679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching' [patent_app_type] => B1 [patent_app_number] => 09/609376 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5051 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381679.pdf [firstpage_image] =>[orig_patent_app_number] => 09609376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609376
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching Jul 2, 2000 Issued
Array ( [id] => 1580277 [patent_doc_number] => 06470413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Information processing apparatus and method in which an executable file in an incorporated memory is loaded and executed at startup' [patent_app_type] => B1 [patent_app_number] => 09/605670 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 43 [patent_no_of_words] => 13529 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470413.pdf [firstpage_image] =>[orig_patent_app_number] => 09605670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605670
Information processing apparatus and method in which an executable file in an incorporated memory is loaded and executed at startup Jun 27, 2000 Issued
Array ( [id] => 1481084 [patent_doc_number] => 06389515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations' [patent_app_type] => B1 [patent_app_number] => 09/597621 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389515.pdf [firstpage_image] =>[orig_patent_app_number] => 09597621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597621
System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations Jun 19, 2000 Issued
Array ( [id] => 1602236 [patent_doc_number] => 06493793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Content addressable memory device having selective cascade logic and method for selectively combining match information in a CAM device' [patent_app_type] => B1 [patent_app_number] => 09/595773 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 12742 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493793.pdf [firstpage_image] =>[orig_patent_app_number] => 09595773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595773
Content addressable memory device having selective cascade logic and method for selectively combining match information in a CAM device Jun 15, 2000 Issued
Array ( [id] => 1423027 [patent_doc_number] => 06522163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Apparatus and method for coupling a first node to a second node using switches which are selectively clocked for fast switching times' [patent_app_type] => B1 [patent_app_number] => 09/578917 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4705 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522163.pdf [firstpage_image] =>[orig_patent_app_number] => 09578917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578917
Apparatus and method for coupling a first node to a second node using switches which are selectively clocked for fast switching times May 24, 2000 Issued
Array ( [id] => 4424094 [patent_doc_number] => 06301636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Content addressable memory system with cascaded memories and self timed signals' [patent_app_type] => 1 [patent_app_number] => 9/572861 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6863 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301636.pdf [firstpage_image] =>[orig_patent_app_number] => 572861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572861
Content addressable memory system with cascaded memories and self timed signals May 17, 2000 Issued
Array ( [id] => 6348794 [patent_doc_number] => 20020035661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'STATE MACHINE HAVING EACH EXECUTION CYCLE DIRECTLY CONNECTED TO A SUSPEND CYCLE TO ACHIEVE FAST SUSPEND OF ERASE OPERATION IN FLASH MEMORIES' [patent_app_type] => new [patent_app_number] => 09/567574 [patent_app_country] => US [patent_app_date] => 2000-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2922 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20020035661.pdf [firstpage_image] =>[orig_patent_app_number] => 09567574 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567574
State machine having each execution cycle directly connected to a suspend cycle to achieve fast suspend of erase operation in flash memories May 9, 2000 Issued
Array ( [id] => 1557448 [patent_doc_number] => 06401148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'FIFO memory system and method with improved determination of amount of data stored using a binary read address synchronized to a write clock' [patent_app_type] => B1 [patent_app_number] => 09/569592 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 14234 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401148.pdf [firstpage_image] =>[orig_patent_app_number] => 09569592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569592
FIFO memory system and method with improved determination of amount of data stored using a binary read address synchronized to a write clock May 8, 2000 Issued
Array ( [id] => 1480902 [patent_doc_number] => 06389490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals' [patent_app_type] => B1 [patent_app_number] => 09/569591 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 13974 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389490.pdf [firstpage_image] =>[orig_patent_app_number] => 09569591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569591
FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals May 8, 2000 Issued
Array ( [id] => 1501475 [patent_doc_number] => 06405269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers' [patent_app_type] => B1 [patent_app_number] => 09/568556 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 13948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405269.pdf [firstpage_image] =>[orig_patent_app_number] => 09568556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/568556
FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers May 8, 2000 Issued
09/539554 METHOD AND COMPUTER READABLE MEDIUM FOR PUSH CACHING DATA IN NETWORK Mar 30, 2000 Abandoned
Array ( [id] => 1409442 [patent_doc_number] => 06557082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method and apparatus for ensuring cache coherency for spawned dependent transactions in a multi-system environment with shared data storage devices' [patent_app_type] => B1 [patent_app_number] => 09/539664 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5702 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557082.pdf [firstpage_image] =>[orig_patent_app_number] => 09539664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539664
Method and apparatus for ensuring cache coherency for spawned dependent transactions in a multi-system environment with shared data storage devices Mar 29, 2000 Issued
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