Danielle Jackson

Array ( [id] => 1409442 [patent_doc_number] => 06557082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method and apparatus for ensuring cache coherency for spawned dependent transactions in a multi-system environment with shared data storage devices' [patent_app_type] => B1 [patent_app_number] => 09/539664 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5702 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557082.pdf [firstpage_image] =>[orig_patent_app_number] => 09539664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1337184 [patent_doc_number] => 06604182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Methods for managing memory in a run-time environment including activation and deactivation of objects' [patent_app_type] => B1 [patent_app_number] => 09/512622 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7664 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604182.pdf [firstpage_image] =>[orig_patent_app_number] => 09512622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1218183 [patent_doc_number] => 06711657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Methods for managing memory in a run-time environment including registration of a deallocation routine at explicit, lazy initialization' [patent_app_type] => B1 [patent_app_number] => 09/512619 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711657.pdf [firstpage_image] =>[orig_patent_app_number] => 09512619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644138 [patent_doc_number] => 06473836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Computing system and cache memory control apparatus controlling prefetch in hierarchical cache memories' [patent_app_type] => B1 [patent_app_number] => 09/513854 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6082 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473836.pdf [firstpage_image] =>[orig_patent_app_number] => 09513854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524892 [patent_doc_number] => 06415363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Memory statistics counter and method for counting the number of accesses to a portion of memory' [patent_app_type] => B1 [patent_app_number] => 09/512407 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2899 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415363.pdf [firstpage_image] =>[orig_patent_app_number] => 09512407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521735 [patent_doc_number] => 06502176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Computer system and methods for loading and modifying a control program without stopping the computer system using reserve areas' [patent_app_type] => B1 [patent_app_number] => 09/511186 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502176.pdf [firstpage_image] =>[orig_patent_app_number] => 09511186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1325289 [patent_doc_number] => 06615331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'System and method to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal' [patent_app_type] => B1 [patent_app_number] => 09/510138 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 3216 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615331.pdf [firstpage_image] =>[orig_patent_app_number] => 09510138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444101 [patent_doc_number] => 06496913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'System and method for detecting and correcting fragmentation on optical storage media' [patent_app_type] => B1 [patent_app_number] => 09/507214 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4343 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496913.pdf [firstpage_image] =>[orig_patent_app_number] => 09507214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423604 [patent_doc_number] => 06539466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'System and method for TLB buddy entry self-timing' [patent_app_type] => B1 [patent_app_number] => 09/510276 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 12736 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539466.pdf [firstpage_image] =>[orig_patent_app_number] => 09510276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1501583 [patent_doc_number] => 06405298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Linear address generator and method for generating a linear address using parallel computations and a single cycle algorithm' [patent_app_type] => B1 [patent_app_number] => 09/510127 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5705 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405298.pdf [firstpage_image] =>[orig_patent_app_number] => 09510127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462407 [patent_doc_number] => 06427189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline' [patent_app_type] => B1 [patent_app_number] => 09/510973 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427189.pdf [firstpage_image] =>[orig_patent_app_number] => 09510973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1214362 [patent_doc_number] => 06715035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency' [patent_app_type] => B1 [patent_app_number] => 09/506506 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4082 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715035.pdf [firstpage_image] =>[orig_patent_app_number] => 09506506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1385794 [patent_doc_number] => 06571312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Data storage method and data processing device using an erasure block buffer and write buffer for writing and erasing data in memory' [patent_app_type] => B1 [patent_app_number] => 09/504713 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 14397 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571312.pdf [firstpage_image] =>[orig_patent_app_number] => 09504713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1291907 [patent_doc_number] => 06643754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'System and method for dynamically allocating computer memory' [patent_app_type] => B1 [patent_app_number] => 09/504610 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 8329 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643754.pdf [firstpage_image] =>[orig_patent_app_number] => 09504610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429806 [patent_doc_number] => 06510496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Shared memory multiprocessor system and method with address translation between partitions and resetting of nodes included in other partitions' [patent_app_type] => B1 [patent_app_number] => 09/501978 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 13130 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510496.pdf [firstpage_image] =>[orig_patent_app_number] => 09501978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376365 [patent_doc_number] => 06219749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Content addressable memory system with self-timed signals and cascaded memories for propagating hit signals' [patent_app_type] => 1 [patent_app_number] => 9/501583 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3285 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219749.pdf [firstpage_image] =>[orig_patent_app_number] => 501583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5990647 [patent_doc_number] => 20020099903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure' [patent_app_type] => new [patent_app_number] => 09/496759 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13841 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099903.pdf [firstpage_image] =>[orig_patent_app_number] => 09496759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424780 [patent_doc_number] => 06230250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Synchronous memory and data processing system having a programmable burst order' [patent_app_type] => 1 [patent_app_number] => 9/457199 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230250.pdf [firstpage_image] =>[orig_patent_app_number] => 457199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310044 [patent_doc_number] => 06212596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Synchronous memory and data processing system having a programmable burst length' [patent_app_type] => 1 [patent_app_number] => 9/454825 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212596.pdf [firstpage_image] =>[orig_patent_app_number] => 454825 [rel_patent_id] =>[rel_patent_doc_number] =>)