Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4424780 [patent_doc_number] => 06230250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Synchronous memory and data processing system having a programmable burst order' [patent_app_type] => 1 [patent_app_number] => 9/457199 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230250.pdf [firstpage_image] =>[orig_patent_app_number] => 457199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457199
Synchronous memory and data processing system having a programmable burst order Dec 5, 1999 Issued
Array ( [id] => 4349834 [patent_doc_number] => 06321316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method and apparatus for local control signal generation in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/444108 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4324 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321316.pdf [firstpage_image] =>[orig_patent_app_number] => 444108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/444108
Method and apparatus for local control signal generation in a memory device Nov 21, 1999 Issued
Array ( [id] => 1471926 [patent_doc_number] => 06460115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism' [patent_app_type] => B1 [patent_app_number] => 09/435865 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6149 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460115.pdf [firstpage_image] =>[orig_patent_app_number] => 09435865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435865
System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism Nov 7, 1999 Issued
Array ( [id] => 7645888 [patent_doc_number] => 06477635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing' [patent_app_type] => B1 [patent_app_number] => 09/435862 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3474 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477635.pdf [firstpage_image] =>[orig_patent_app_number] => 09435862 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435862
Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing Nov 7, 1999 Issued
Array ( [id] => 1339187 [patent_doc_number] => 06601139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Information processing method and apparatus using a storage medium storing all necessary software and content to configure and operate the apparatus' [patent_app_type] => B1 [patent_app_number] => 09/433990 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14239 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601139.pdf [firstpage_image] =>[orig_patent_app_number] => 09433990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433990
Information processing method and apparatus using a storage medium storing all necessary software and content to configure and operate the apparatus Nov 3, 1999 Issued
Array ( [id] => 1604476 [patent_doc_number] => 06434662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System and method for searching an associative memory utilizing first and second hash functions' [patent_app_type] => B1 [patent_app_number] => 09/432138 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7042 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434662.pdf [firstpage_image] =>[orig_patent_app_number] => 09432138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432138
System and method for searching an associative memory utilizing first and second hash functions Nov 1, 1999 Issued
Array ( [id] => 1258340 [patent_doc_number] => 06671768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'System and method for providing dynamic configuration ROM using double image buffers for use with serial bus devices' [patent_app_type] => B1 [patent_app_number] => 09/431409 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5884 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671768.pdf [firstpage_image] =>[orig_patent_app_number] => 09431409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431409
System and method for providing dynamic configuration ROM using double image buffers for use with serial bus devices Oct 31, 1999 Issued
Array ( [id] => 1567331 [patent_doc_number] => 06438651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method, system, and program for managing requests to a cache using flags to queue and dequeue data in a buffer' [patent_app_type] => B1 [patent_app_number] => 09/432044 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4999 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438651.pdf [firstpage_image] =>[orig_patent_app_number] => 09432044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432044
Method, system, and program for managing requests to a cache using flags to queue and dequeue data in a buffer Oct 31, 1999 Issued
09/431715 METHOD AND SYSTEM FOR PARTITIONING A STORAGE ARRAY AMONG MULTIPLE HOSTS IN A STORAGE ARRAY NETWORK AND COMPUTER READABLE MEDIUM FOR MAPPING A LUN TO A VOLUME Oct 27, 1999 Abandoned
Array ( [id] => 1567401 [patent_doc_number] => 06438664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Microcode patch device and method for patching microcode using match registers and patch routines' [patent_app_type] => B1 [patent_app_number] => 09/428635 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13588 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438664.pdf [firstpage_image] =>[orig_patent_app_number] => 09428635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428635
Microcode patch device and method for patching microcode using match registers and patch routines Oct 26, 1999 Issued
Array ( [id] => 1567294 [patent_doc_number] => 06438644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method to prevent a flash memory from being miswritten' [patent_app_type] => B1 [patent_app_number] => 09/427112 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2414 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438644.pdf [firstpage_image] =>[orig_patent_app_number] => 09427112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427112
Method to prevent a flash memory from being miswritten Oct 25, 1999 Issued
Array ( [id] => 1549545 [patent_doc_number] => 06374326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Multiple bank CAM architecture and method for performing concurrent lookup operations' [patent_app_type] => B1 [patent_app_number] => 09/426574 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3509 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374326.pdf [firstpage_image] =>[orig_patent_app_number] => 09426574 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426574
Multiple bank CAM architecture and method for performing concurrent lookup operations Oct 24, 1999 Issued
Array ( [id] => 6388845 [patent_doc_number] => 20020120812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'REDUNDANT RECORDING DISK DEVICE AND DATA PROCESSING METHOD USING PLURAL LOGICAL DISKS WITH MIRRORED DATA STORED WITH A PREDETERMINED PHASE-OFFSET' [patent_app_type] => new [patent_app_number] => 09/422463 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6243 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120812.pdf [firstpage_image] =>[orig_patent_app_number] => 09422463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422463
Redundant recording disk device and data processing method using plural logical disks with mirrored data stored with a predetermined phase-offset Oct 20, 1999 Issued
Array ( [id] => 1459993 [patent_doc_number] => 06463501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method, system and program for maintaining data consistency among updates across groups of storage areas using update times' [patent_app_type] => B1 [patent_app_number] => 09/422595 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6162 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463501.pdf [firstpage_image] =>[orig_patent_app_number] => 09422595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422595
Method, system and program for maintaining data consistency among updates across groups of storage areas using update times Oct 20, 1999 Issued
Array ( [id] => 1604456 [patent_doc_number] => 06434642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'FIFO memory system and method with improved determination of full and empty conditions and amount of data stored' [patent_app_type] => B1 [patent_app_number] => 09/414987 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 13944 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434642.pdf [firstpage_image] =>[orig_patent_app_number] => 09414987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414987
FIFO memory system and method with improved determination of full and empty conditions and amount of data stored Oct 6, 1999 Issued
Array ( [id] => 1456775 [patent_doc_number] => 06457108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/415032 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6283 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457108.pdf [firstpage_image] =>[orig_patent_app_number] => 09415032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415032
Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory Oct 6, 1999 Issued
Array ( [id] => 1365386 [patent_doc_number] => 06581146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration' [patent_app_type] => B1 [patent_app_number] => 09/401886 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3229 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581146.pdf [firstpage_image] =>[orig_patent_app_number] => 09401886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401886
Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration Sep 22, 1999 Issued
Array ( [id] => 1462438 [patent_doc_number] => 06427196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'SRAM controller for parallel processor architecture including address and command queue and arbiter' [patent_app_type] => B1 [patent_app_number] => 09/387110 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11076 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427196.pdf [firstpage_image] =>[orig_patent_app_number] => 09387110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387110
SRAM controller for parallel processor architecture including address and command queue and arbiter Aug 30, 1999 Issued
Array ( [id] => 1604480 [patent_doc_number] => 06434666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Memory control apparatus and method for storing data in a selected cache memory based on whether a group or slot number is odd or even' [patent_app_type] => B1 [patent_app_number] => 09/370998 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4703 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434666.pdf [firstpage_image] =>[orig_patent_app_number] => 09370998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370998
Memory control apparatus and method for storing data in a selected cache memory based on whether a group or slot number is odd or even Aug 9, 1999 Issued
Array ( [id] => 7626829 [patent_doc_number] => 06807615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Apparatus and method for providing a cyclic buffer using logical blocks' [patent_app_type] => B1 [patent_app_number] => 09/288023 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5183 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807615.pdf [firstpage_image] =>[orig_patent_app_number] => 09288023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/288023
Apparatus and method for providing a cyclic buffer using logical blocks Apr 7, 1999 Issued
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