Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4388102 [patent_doc_number] => 06275899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method and circuit for implementing digital delay lines using delay caches' [patent_app_type] => 1 [patent_app_number] => 9/191754 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6000 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275899.pdf [firstpage_image] =>[orig_patent_app_number] => 191754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191754
Method and circuit for implementing digital delay lines using delay caches Nov 12, 1998 Issued
Array ( [id] => 1572379 [patent_doc_number] => 06378048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'SLIME cache coherency system for agents with multi-layer caches' [patent_app_type] => B1 [patent_app_number] => 09/190126 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4619 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378048.pdf [firstpage_image] =>[orig_patent_app_number] => 09190126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190126
SLIME cache coherency system for agents with multi-layer caches Nov 11, 1998 Issued
Array ( [id] => 4298718 [patent_doc_number] => 06282624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Non-volatile memory apparatus including first and second address conversion tables stored in volatile and nonvolatile memories for improved access at power up' [patent_app_type] => 1 [patent_app_number] => 9/191437 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 17629 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282624.pdf [firstpage_image] =>[orig_patent_app_number] => 191437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191437
Non-volatile memory apparatus including first and second address conversion tables stored in volatile and nonvolatile memories for improved access at power up Nov 11, 1998 Issued
Array ( [id] => 4121938 [patent_doc_number] => 06052759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method for organizing storage devices of unequal storage capacity and distributing data using different raid formats depending on size of rectangles containing sets of the storage devices' [patent_app_type] => 1 [patent_app_number] => 9/191717 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 13614 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052759.pdf [firstpage_image] =>[orig_patent_app_number] => 191717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191717
Method for organizing storage devices of unequal storage capacity and distributing data using different raid formats depending on size of rectangles containing sets of the storage devices Nov 11, 1998 Issued
Array ( [id] => 4280784 [patent_doc_number] => 06260113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and apparatus defining a miss list and producing dial-in hit ratios in a disk storage benchmark' [patent_app_type] => 1 [patent_app_number] => 9/190923 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5752 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260113.pdf [firstpage_image] =>[orig_patent_app_number] => 190923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190923
Method and apparatus defining a miss list and producing dial-in hit ratios in a disk storage benchmark Nov 11, 1998 Issued
09/183617 DUAL READ PROTOCOLS FOR AN EXTERNAL MEMORY IN A MICROCONTROLLER ENVIRONMENT Oct 29, 1998 Abandoned
Array ( [id] => 1572245 [patent_doc_number] => 06378018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Memory device and system including a low power interface' [patent_app_type] => B1 [patent_app_number] => 09/169506 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 4109 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378018.pdf [firstpage_image] =>[orig_patent_app_number] => 09169506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169506
Memory device and system including a low power interface Oct 8, 1998 Issued
09/155618 INFORMATION PROCESSING APPARATUS AND METHOD Sep 28, 1998 Abandoned
Array ( [id] => 1568668 [patent_doc_number] => 06339817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Semiconductor memory including main and sub memory portions having plural memory cell groups and a bidirectional data transfer circuit' [patent_app_type] => B1 [patent_app_number] => 09/153534 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 100 [patent_figures_cnt] => 100 [patent_no_of_words] => 23895 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339817.pdf [firstpage_image] =>[orig_patent_app_number] => 09153534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153534
Semiconductor memory including main and sub memory portions having plural memory cell groups and a bidirectional data transfer circuit Sep 15, 1998 Issued
Array ( [id] => 4279877 [patent_doc_number] => 06205524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Multimedia arbiter and method using fixed round-robin slots for real-time agents and a timed priority slot for non-real-time agents' [patent_app_type] => 1 [patent_app_number] => 9/153950 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205524.pdf [firstpage_image] =>[orig_patent_app_number] => 153950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153950
Multimedia arbiter and method using fixed round-robin slots for real-time agents and a timed priority slot for non-real-time agents Sep 15, 1998 Issued
Array ( [id] => 4381143 [patent_doc_number] => 06256702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Nonvolatile memory device with extended storage and high reliability through writing the same data into two memory cells' [patent_app_type] => 1 [patent_app_number] => 9/150808 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7110 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256702.pdf [firstpage_image] =>[orig_patent_app_number] => 150808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150808
Nonvolatile memory device with extended storage and high reliability through writing the same data into two memory cells Sep 9, 1998 Issued
Array ( [id] => 4422608 [patent_doc_number] => 06173380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Apparatus and method for providing multiple channel clock-data alignment' [patent_app_type] => 1 [patent_app_number] => 9/118700 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7650 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173380.pdf [firstpage_image] =>[orig_patent_app_number] => 118700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118700
Apparatus and method for providing multiple channel clock-data alignment Jul 15, 1998 Issued
Array ( [id] => 4323892 [patent_doc_number] => 06189076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal' [patent_app_type] => 1 [patent_app_number] => 9/102777 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189076.pdf [firstpage_image] =>[orig_patent_app_number] => 102777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102777
Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal Jun 22, 1998 Issued
Array ( [id] => 4424736 [patent_doc_number] => 06230240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface' [patent_app_type] => 1 [patent_app_number] => 9/103329 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5289 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230240.pdf [firstpage_image] =>[orig_patent_app_number] => 103329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103329
Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface Jun 22, 1998 Issued
Array ( [id] => 1409263 [patent_doc_number] => 06557071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage' [patent_app_type] => B2 [patent_app_number] => 09/102096 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3300 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557071.pdf [firstpage_image] =>[orig_patent_app_number] => 09102096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102096
Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage Jun 21, 1998 Issued
Array ( [id] => 1443885 [patent_doc_number] => 06336160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method and system for dividing a computer processor register into sectors and storing frequently used values therein' [patent_app_type] => B1 [patent_app_number] => 09/100717 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3373 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336160.pdf [firstpage_image] =>[orig_patent_app_number] => 09100717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100717
Method and system for dividing a computer processor register into sectors and storing frequently used values therein Jun 18, 1998 Issued
Array ( [id] => 6908568 [patent_doc_number] => 20010011335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'DATA PROCESSING SYSTEM HAVING A NETWORK AND METHOD FOR MANAGING MEMORY BY STORING DISCARDABLE PAGES IN A LOCAL PAGING DEVICE' [patent_app_type] => new [patent_app_number] => 09/100460 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3303 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011335.pdf [firstpage_image] =>[orig_patent_app_number] => 09100460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100460
Data processing system having a network and method for managing memory by storing discardable pages in a local paging device Jun 18, 1998 Issued
Array ( [id] => 4373853 [patent_doc_number] => 06202139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing' [patent_app_type] => 1 [patent_app_number] => 9/100291 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8091 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202139.pdf [firstpage_image] =>[orig_patent_app_number] => 100291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100291
Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing Jun 18, 1998 Issued
Array ( [id] => 4423342 [patent_doc_number] => 06311250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Computer memory controller with self refresh performed during memory back-up operation in case of power failure' [patent_app_type] => 1 [patent_app_number] => 9/100329 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2644 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311250.pdf [firstpage_image] =>[orig_patent_app_number] => 100329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100329
Computer memory controller with self refresh performed during memory back-up operation in case of power failure Jun 18, 1998 Issued
09/092890 REDUNDANT FORM ADDRESS DECODER FOR MEMORY SYSTEM STORING ALIGNED DATA Jun 7, 1998 Abandoned
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