Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4304697 [patent_doc_number] => 06269424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Disk array device with selectable method for generating redundant data' [patent_app_type] => 1 [patent_app_number] => 8/974535 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8085 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269424.pdf [firstpage_image] =>[orig_patent_app_number] => 974535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974535
Disk array device with selectable method for generating redundant data Nov 18, 1997 Issued
Array ( [id] => 4427284 [patent_doc_number] => 06226707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line' [patent_app_type] => 1 [patent_app_number] => 8/972054 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3798 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226707.pdf [firstpage_image] =>[orig_patent_app_number] => 972054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972054
System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line Nov 16, 1997 Issued
Array ( [id] => 4317799 [patent_doc_number] => 06185664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for providing additional latency for synchronously accessed memory' [patent_app_type] => 1 [patent_app_number] => 8/971834 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3521 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185664.pdf [firstpage_image] =>[orig_patent_app_number] => 971834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971834
Method for providing additional latency for synchronously accessed memory Nov 16, 1997 Issued
Array ( [id] => 1297106 [patent_doc_number] => 06633958 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure' [patent_app_type] => B1 [patent_app_number] => 08/971184 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6380 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633958.pdf [firstpage_image] =>[orig_patent_app_number] => 08971184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971184
Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure Nov 16, 1997 Issued
Array ( [id] => 4257731 [patent_doc_number] => 06145066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Computer system with transparent data migration between storage volumes' [patent_app_type] => 1 [patent_app_number] => 8/971473 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 9331 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145066.pdf [firstpage_image] =>[orig_patent_app_number] => 971473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971473
Computer system with transparent data migration between storage volumes Nov 13, 1997 Issued
Array ( [id] => 1116631 [patent_doc_number] => 06804766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method for managing pages of a designated memory object according to selected memory management policies' [patent_app_type] => B1 [patent_app_number] => 08/968244 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 18592 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804766.pdf [firstpage_image] =>[orig_patent_app_number] => 08968244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968244
Method for managing pages of a designated memory object according to selected memory management policies Nov 11, 1997 Issued
Array ( [id] => 4239089 [patent_doc_number] => 06088777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages' [patent_app_type] => 1 [patent_app_number] => 8/968514 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8108 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088777.pdf [firstpage_image] =>[orig_patent_app_number] => 968514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968514
Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages Nov 11, 1997 Issued
Array ( [id] => 4211222 [patent_doc_number] => 06044432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Method and system for latching an address for accessing synchronous random access memory using a single address status signal control line' [patent_app_type] => 1 [patent_app_number] => 8/968555 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3489 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044432.pdf [firstpage_image] =>[orig_patent_app_number] => 968555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968555
Method and system for latching an address for accessing synchronous random access memory using a single address status signal control line Nov 11, 1997 Issued
Array ( [id] => 4259794 [patent_doc_number] => 06092154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method of pre-caching or pre-fetching data utilizing thread lists and multimedia editing systems using such pre-caching' [patent_app_type] => 1 [patent_app_number] => 8/966771 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5956 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092154.pdf [firstpage_image] =>[orig_patent_app_number] => 966771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966771
Method of pre-caching or pre-fetching data utilizing thread lists and multimedia editing systems using such pre-caching Nov 6, 1997 Issued
Array ( [id] => 4374658 [patent_doc_number] => 06170040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Superscalar processor employing a high performance write back buffer controlled by a state machine to reduce write cycles' [patent_app_type] => 1 [patent_app_number] => 8/964133 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4753 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170040.pdf [firstpage_image] =>[orig_patent_app_number] => 964133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964133
Superscalar processor employing a high performance write back buffer controlled by a state machine to reduce write cycles Nov 5, 1997 Issued
Array ( [id] => 4121953 [patent_doc_number] => 06052760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks' [patent_app_type] => 1 [patent_app_number] => 8/964626 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5798 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052760.pdf [firstpage_image] =>[orig_patent_app_number] => 964626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964626
Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks Nov 4, 1997 Issued
Array ( [id] => 4259821 [patent_doc_number] => 06092156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations' [patent_app_type] => 1 [patent_app_number] => 8/964623 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6631 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092156.pdf [firstpage_image] =>[orig_patent_app_number] => 964623 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964623
System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations Nov 4, 1997 Issued
08/965004 DIRECTORY-BASED CACHE COHERENCY SYSTEM Nov 4, 1997 Abandoned
Array ( [id] => 4257048 [patent_doc_number] => 06081879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Data processing system and virtual partitioning method for creating logical multi-level units of online storage' [patent_app_type] => 1 [patent_app_number] => 8/963899 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3756 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081879.pdf [firstpage_image] =>[orig_patent_app_number] => 963899 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963899
Data processing system and virtual partitioning method for creating logical multi-level units of online storage Nov 3, 1997 Issued
Array ( [id] => 4133177 [patent_doc_number] => 06047358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups' [patent_app_type] => 1 [patent_app_number] => 8/961965 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10990 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047358.pdf [firstpage_image] =>[orig_patent_app_number] => 961965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961965
Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups Oct 30, 1997 Issued
Array ( [id] => 3961556 [patent_doc_number] => 05974508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Cache memory system and method for automatically locking cache entries to prevent selected memory items from being replaced' [patent_app_type] => 1 [patent_app_number] => 8/947188 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4802 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974508.pdf [firstpage_image] =>[orig_patent_app_number] => 947188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947188
Cache memory system and method for automatically locking cache entries to prevent selected memory items from being replaced Oct 7, 1997 Issued
Array ( [id] => 4374071 [patent_doc_number] => 06175896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Microprocessor system and method for increasing memory Bandwidth for data transfers between a cache and main memory utilizing data compression' [patent_app_type] => 1 [patent_app_number] => 8/944691 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3908 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175896.pdf [firstpage_image] =>[orig_patent_app_number] => 944691 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944691
Microprocessor system and method for increasing memory Bandwidth for data transfers between a cache and main memory utilizing data compression Oct 5, 1997 Issued
Array ( [id] => 4202492 [patent_doc_number] => 06094713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method and apparatus for detecting address range overlaps' [patent_app_type] => 1 [patent_app_number] => 8/940167 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2877 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094713.pdf [firstpage_image] =>[orig_patent_app_number] => 940167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940167
Method and apparatus for detecting address range overlaps Sep 29, 1997 Issued
Array ( [id] => 4099838 [patent_doc_number] => 06055603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method and apparatus for performing pre-request operations in a cached disk array storage system' [patent_app_type] => 1 [patent_app_number] => 8/932660 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3977 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055603.pdf [firstpage_image] =>[orig_patent_app_number] => 932660 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932660
Method and apparatus for performing pre-request operations in a cached disk array storage system Sep 17, 1997 Issued
Array ( [id] => 4099983 [patent_doc_number] => 06055613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'System and method for transferring data and status information between memories of different types occupying a single real address space using a dedicated memory transfer bus' [patent_app_type] => 1 [patent_app_number] => 8/928221 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4030 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055613.pdf [firstpage_image] =>[orig_patent_app_number] => 928221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928221
System and method for transferring data and status information between memories of different types occupying a single real address space using a dedicated memory transfer bus Sep 11, 1997 Issued
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