| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4155852
[patent_doc_number] => 06122707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Content addressable memory system with self-timed signals and cascaded memories for propagating hit signals'
[patent_app_type] => 1
[patent_app_number] => 8/923633
[patent_app_country] => US
[patent_app_date] => 1997-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2989
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122707.pdf
[firstpage_image] =>[orig_patent_app_number] => 923633
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/923633 | Content addressable memory system with self-timed signals and cascaded memories for propagating hit signals | Sep 3, 1997 | Issued |
Array
(
[id] => 3970660
[patent_doc_number] => 05991863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Single carry/borrow propagate adder/decrementer for generating register stack addresses in a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/920729
[patent_app_country] => US
[patent_app_date] => 1997-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 11816
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/991/05991863.pdf
[firstpage_image] =>[orig_patent_app_number] => 920729
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/920729 | Single carry/borrow propagate adder/decrementer for generating register stack addresses in a microprocessor | Aug 28, 1997 | Issued |
Array
(
[id] => 4424721
[patent_doc_number] => 06230236
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Content addressable memory system with cascaded memories and self timed signals'
[patent_app_type] => 1
[patent_app_number] => 8/919227
[patent_app_country] => US
[patent_app_date] => 1997-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 23
[patent_no_of_words] => 6624
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/230/06230236.pdf
[firstpage_image] =>[orig_patent_app_number] => 919227
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919227 | Content addressable memory system with cascaded memories and self timed signals | Aug 27, 1997 | Issued |
Array
(
[id] => 4126683
[patent_doc_number] => 06058453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method and apparatus for subcode/data synchronization in a compact disc system'
[patent_app_type] => 1
[patent_app_number] => 8/914298
[patent_app_country] => US
[patent_app_date] => 1997-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 7869
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/058/06058453.pdf
[firstpage_image] =>[orig_patent_app_number] => 914298
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914298 | Method and apparatus for subcode/data synchronization in a compact disc system | Aug 17, 1997 | Issued |
Array
(
[id] => 4280756
[patent_doc_number] => 06260111
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'System and method for network power management incorporating user identity and preferences via a power managed smart card'
[patent_app_type] => 1
[patent_app_number] => 8/911863
[patent_app_country] => US
[patent_app_date] => 1997-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4561
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/260/06260111.pdf
[firstpage_image] =>[orig_patent_app_number] => 911863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911863 | System and method for network power management incorporating user identity and preferences via a power managed smart card | Aug 14, 1997 | Issued |
Array
(
[id] => 1377118
[patent_doc_number] => 06578124
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration'
[patent_app_type] => B1
[patent_app_number] => 08/908242
[patent_app_country] => US
[patent_app_date] => 1997-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3211
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/578/06578124.pdf
[firstpage_image] =>[orig_patent_app_number] => 08908242
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/908242 | Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration | Aug 6, 1997 | Issued |
Array
(
[id] => 4148729
[patent_doc_number] => 06016534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Data processing system for controlling operation of a sense amplifier in a cache'
[patent_app_type] => 1
[patent_app_number] => 8/887825
[patent_app_country] => US
[patent_app_date] => 1997-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3560
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/016/06016534.pdf
[firstpage_image] =>[orig_patent_app_number] => 887825
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/887825 | Data processing system for controlling operation of a sense amplifier in a cache | Jul 29, 1997 | Issued |
Array
(
[id] => 4138911
[patent_doc_number] => 06073223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory'
[patent_app_type] => 1
[patent_app_number] => 8/897444
[patent_app_country] => US
[patent_app_date] => 1997-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3120
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/073/06073223.pdf
[firstpage_image] =>[orig_patent_app_number] => 897444
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897444 | Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory | Jul 20, 1997 | Issued |
Array
(
[id] => 4179295
[patent_doc_number] => 06115799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Information processing apparatus and associated method for managing a memory using a next fit and for reducing a memory fragmentation problem'
[patent_app_type] => 1
[patent_app_number] => 8/897546
[patent_app_country] => US
[patent_app_date] => 1997-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 43
[patent_no_of_words] => 13558
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/115/06115799.pdf
[firstpage_image] =>[orig_patent_app_number] => 897546
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897546 | Information processing apparatus and associated method for managing a memory using a next fit and for reducing a memory fragmentation problem | Jul 20, 1997 | Issued |
Array
(
[id] => 4194936
[patent_doc_number] => 06085289
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Method and system for load data formatting and improved method for cache line organization'
[patent_app_type] => 1
[patent_app_number] => 8/896475
[patent_app_country] => US
[patent_app_date] => 1997-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2913
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/085/06085289.pdf
[firstpage_image] =>[orig_patent_app_number] => 896475
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896475 | Method and system for load data formatting and improved method for cache line organization | Jul 17, 1997 | Issued |
Array
(
[id] => 4026890
[patent_doc_number] => 05890201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Content addressable memory having memory cells storing don\'t care states for address translation'
[patent_app_type] => 1
[patent_app_number] => 8/886761
[patent_app_country] => US
[patent_app_date] => 1997-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 8671
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 440
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/890/05890201.pdf
[firstpage_image] =>[orig_patent_app_number] => 886761
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/886761 | Content addressable memory having memory cells storing don't care states for address translation | Jun 30, 1997 | Issued |
Array
(
[id] => 3932792
[patent_doc_number] => 06003112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Memory controller and method for clearing or copying memory utilizing register files to store address information'
[patent_app_type] => 1
[patent_app_number] => 8/886079
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4219
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/003/06003112.pdf
[firstpage_image] =>[orig_patent_app_number] => 886079
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/886079 | Memory controller and method for clearing or copying memory utilizing register files to store address information | Jun 29, 1997 | Issued |
Array
(
[id] => 4273426
[patent_doc_number] => 06209056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Semiconductor memory device having a plurality of bank sections distributed in a plurality of divided memory cell arrays'
[patent_app_type] => 1
[patent_app_number] => 8/885035
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3191
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/209/06209056.pdf
[firstpage_image] =>[orig_patent_app_number] => 885035
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885035 | Semiconductor memory device having a plurality of bank sections distributed in a plurality of divided memory cell arrays | Jun 29, 1997 | Issued |
Array
(
[id] => 4423359
[patent_doc_number] => 06311252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Method and apparatus for moving data between storage levels of a hierarchically arranged data storage system'
[patent_app_type] => 1
[patent_app_number] => 8/885263
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3653
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/311/06311252.pdf
[firstpage_image] =>[orig_patent_app_number] => 885263
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885263 | Method and apparatus for moving data between storage levels of a hierarchically arranged data storage system | Jun 29, 1997 | Issued |
Array
(
[id] => 4103659
[patent_doc_number] => 06026464
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Memory control system and method utilizing distributed memory controllers for multibank memory'
[patent_app_type] => 1
[patent_app_number] => 8/881551
[patent_app_country] => US
[patent_app_date] => 1997-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3635
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/026/06026464.pdf
[firstpage_image] =>[orig_patent_app_number] => 881551
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881551 | Memory control system and method utilizing distributed memory controllers for multibank memory | Jun 23, 1997 | Issued |
Array
(
[id] => 3973328
[patent_doc_number] => 05978884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Semiconductor memory device having a single line data bus and latch circuits for improved pipeline operations'
[patent_app_type] => 1
[patent_app_number] => 8/880890
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13070
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/978/05978884.pdf
[firstpage_image] =>[orig_patent_app_number] => 880890
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880890 | Semiconductor memory device having a single line data bus and latch circuits for improved pipeline operations | Jun 22, 1997 | Issued |
Array
(
[id] => 4085280
[patent_doc_number] => 06009501
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Method and apparatus for local control signal generation in a memory device'
[patent_app_type] => 1
[patent_app_number] => 8/877957
[patent_app_country] => US
[patent_app_date] => 1997-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4335
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/009/06009501.pdf
[firstpage_image] =>[orig_patent_app_number] => 877957
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/877957 | Method and apparatus for local control signal generation in a memory device | Jun 17, 1997 | Issued |
Array
(
[id] => 4099815
[patent_doc_number] => 06055601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Data receiving apparatus capable of writing only necessary data in a file at the time of data reception'
[patent_app_type] => 1
[patent_app_number] => 8/849594
[patent_app_country] => US
[patent_app_date] => 1997-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3664
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/055/06055601.pdf
[firstpage_image] =>[orig_patent_app_number] => 849594
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/849594 | Data receiving apparatus capable of writing only necessary data in a file at the time of data reception | May 27, 1997 | Issued |
Array
(
[id] => 3813187
[patent_doc_number] => 05828862
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Game programming flash memory cartridge system including a programmer and a reprogrammable cartridge'
[patent_app_type] => 1
[patent_app_number] => 8/855478
[patent_app_country] => US
[patent_app_date] => 1997-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 7627
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828862.pdf
[firstpage_image] =>[orig_patent_app_number] => 855478
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/855478 | Game programming flash memory cartridge system including a programmer and a reprogrammable cartridge | May 12, 1997 | Issued |
Array
(
[id] => 4124024
[patent_doc_number] => 06101584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory'
[patent_app_type] => 1
[patent_app_number] => 8/850703
[patent_app_country] => US
[patent_app_date] => 1997-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 93
[patent_no_of_words] => 16794
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/101/06101584.pdf
[firstpage_image] =>[orig_patent_app_number] => 850703
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850703 | Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory | May 1, 1997 | Issued |