Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4052288 [patent_doc_number] => 05943692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Mobile client computer system with flash memory management utilizing a virtual address map and variable length data' [patent_app_type] => 1 [patent_app_number] => 8/848372 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9280 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943692.pdf [firstpage_image] =>[orig_patent_app_number] => 848372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848372
Mobile client computer system with flash memory management utilizing a virtual address map and variable length data Apr 29, 1997 Issued
Array ( [id] => 4100991 [patent_doc_number] => 06018794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Data processing apparatus and method for generating timing signals for a self-timed circuit' [patent_app_type] => 1 [patent_app_number] => 8/841594 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6803 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018794.pdf [firstpage_image] =>[orig_patent_app_number] => 841594 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841594
Data processing apparatus and method for generating timing signals for a self-timed circuit Apr 29, 1997 Issued
Array ( [id] => 7629995 [patent_doc_number] => 06636944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Associative cache and method for replacing data entries having an IO state' [patent_app_type] => B1 [patent_app_number] => 08/850660 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636944.pdf [firstpage_image] =>[orig_patent_app_number] => 08850660 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850660
Associative cache and method for replacing data entries having an IO state Apr 23, 1997 Issued
Array ( [id] => 3969355 [patent_doc_number] => 05956742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Methods for queuing and absorbing erase commands in a nonvolatile memory device' [patent_app_type] => 1 [patent_app_number] => 8/818957 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9090 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956742.pdf [firstpage_image] =>[orig_patent_app_number] => 818957 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818957
Methods for queuing and absorbing erase commands in a nonvolatile memory device Mar 13, 1997 Issued
Array ( [id] => 3765240 [patent_doc_number] => 05802555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method' [patent_app_type] => 1 [patent_app_number] => 8/816460 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 33532 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802555.pdf [firstpage_image] =>[orig_patent_app_number] => 816460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816460
Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method Mar 12, 1997 Issued
Array ( [id] => 3872364 [patent_doc_number] => 05768560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Dynamically configurable memory system having a programmable controller including a frequency multiplier to maintain memory timing resolution for different bus speeds' [patent_app_type] => 1 [patent_app_number] => 8/807898 [patent_app_country] => US [patent_app_date] => 1997-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 19056 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768560.pdf [firstpage_image] =>[orig_patent_app_number] => 807898 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807898
Dynamically configurable memory system having a programmable controller including a frequency multiplier to maintain memory timing resolution for different bus speeds Feb 26, 1997 Issued
Array ( [id] => 4007012 [patent_doc_number] => 05960465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Apparatus and method for directly accessing compressed data utilizing a compressed memory address translation unit and compression descriptor table' [patent_app_type] => 1 [patent_app_number] => 8/807477 [patent_app_country] => US [patent_app_date] => 1997-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8445 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960465.pdf [firstpage_image] =>[orig_patent_app_number] => 807477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807477
Apparatus and method for directly accessing compressed data utilizing a compressed memory address translation unit and compression descriptor table Feb 26, 1997 Issued
Array ( [id] => 3830130 [patent_doc_number] => 05812816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'System and method for transferring data between memories of different types occupying a single real address space using a dedicated memory transfer bus' [patent_app_type] => 1 [patent_app_number] => 8/806860 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4033 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812816.pdf [firstpage_image] =>[orig_patent_app_number] => 806860 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806860
System and method for transferring data between memories of different types occupying a single real address space using a dedicated memory transfer bus Feb 25, 1997 Issued
Array ( [id] => 3901060 [patent_doc_number] => 05897661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Logical volume manager and method having enhanced update capability with dynamic allocation of storage and minimal storage of metadata information' [patent_app_type] => 1 [patent_app_number] => 8/806180 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 8928 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897661.pdf [firstpage_image] =>[orig_patent_app_number] => 806180 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806180
Logical volume manager and method having enhanced update capability with dynamic allocation of storage and minimal storage of metadata information Feb 24, 1997 Issued
Array ( [id] => 4179249 [patent_doc_number] => 06115796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions' [patent_app_type] => 1 [patent_app_number] => 8/806524 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2789 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115796.pdf [firstpage_image] =>[orig_patent_app_number] => 806524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806524
Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions Feb 23, 1997 Issued
Array ( [id] => 4011044 [patent_doc_number] => 05920888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Cache memory system having high and low speed and power consumption modes in which different ways are selectively enabled depending on a reference clock frequency' [patent_app_type] => 1 [patent_app_number] => 8/837876 [patent_app_country] => US [patent_app_date] => 1997-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4806 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920888.pdf [firstpage_image] =>[orig_patent_app_number] => 837876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837876
Cache memory system having high and low speed and power consumption modes in which different ways are selectively enabled depending on a reference clock frequency Feb 11, 1997 Issued
Array ( [id] => 3758708 [patent_doc_number] => 05787464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Computer system including a dual memory configuration which supports on-line memory extraction and insertion' [patent_app_type] => 1 [patent_app_number] => 8/794604 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 3203 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787464.pdf [firstpage_image] =>[orig_patent_app_number] => 794604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794604
Computer system including a dual memory configuration which supports on-line memory extraction and insertion Feb 2, 1997 Issued
Array ( [id] => 4101080 [patent_doc_number] => 06163832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Semiconductor memory device including plural blocks with a pipeline operation for carrying out operations in predetermined order' [patent_app_type] => 1 [patent_app_number] => 8/790964 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 78 [patent_no_of_words] => 13434 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163832.pdf [firstpage_image] =>[orig_patent_app_number] => 790964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790964
Semiconductor memory device including plural blocks with a pipeline operation for carrying out operations in predetermined order Jan 28, 1997 Issued
Array ( [id] => 3996027 [patent_doc_number] => 05918246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Apparatus and method for prefetching data based on information contained in a compiler generated program map' [patent_app_type] => 1 [patent_app_number] => 8/788870 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4777 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918246.pdf [firstpage_image] =>[orig_patent_app_number] => 788870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788870
Apparatus and method for prefetching data based on information contained in a compiler generated program map Jan 22, 1997 Issued
Array ( [id] => 4032527 [patent_doc_number] => 05907853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method and apparatus for maintaining duplicate cache tags with selectable width' [patent_app_type] => 1 [patent_app_number] => 8/783918 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3639 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907853.pdf [firstpage_image] =>[orig_patent_app_number] => 783918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783918
Method and apparatus for maintaining duplicate cache tags with selectable width Jan 16, 1997 Issued
Array ( [id] => 3973358 [patent_doc_number] => 05978886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache' [patent_app_type] => 1 [patent_app_number] => 8/785371 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3465 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978886.pdf [firstpage_image] =>[orig_patent_app_number] => 785371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785371
Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache Jan 16, 1997 Issued
Array ( [id] => 3955076 [patent_doc_number] => 05940848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Computer system and method for efficiently controlling the opening and closing of pages for an aborted row on page miss cycle' [patent_app_type] => 1 [patent_app_number] => 8/783018 [patent_app_country] => US [patent_app_date] => 1997-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5320 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940848.pdf [firstpage_image] =>[orig_patent_app_number] => 783018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783018
Computer system and method for efficiently controlling the opening and closing of pages for an aborted row on page miss cycle Jan 13, 1997 Issued
Array ( [id] => 3970585 [patent_doc_number] => 05958072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware' [patent_app_type] => 1 [patent_app_number] => 8/782964 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4295 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958072.pdf [firstpage_image] =>[orig_patent_app_number] => 782964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782964
Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware Jan 12, 1997 Issued
Array ( [id] => 1495291 [patent_doc_number] => 06418506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array' [patent_app_type] => B1 [patent_app_number] => 08/777898 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5388 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418506.pdf [firstpage_image] =>[orig_patent_app_number] => 08777898 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777898
Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array Dec 30, 1996 Issued
Array ( [id] => 4374594 [patent_doc_number] => 06170036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM' [patent_app_type] => 1 [patent_app_number] => 8/780066 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 93 [patent_figures_cnt] => 117 [patent_no_of_words] => 44681 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170036.pdf [firstpage_image] =>[orig_patent_app_number] => 780066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780066
Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM Dec 22, 1996 Issued
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