Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4033536 [patent_doc_number] => 05963970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for tracking erase cycles utilizing active and inactive wear bar blocks having first and second count fields' [patent_app_type] => 1 [patent_app_number] => 8/770958 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3880 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963970.pdf [firstpage_image] =>[orig_patent_app_number] => 770958 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770958
Method and apparatus for tracking erase cycles utilizing active and inactive wear bar blocks having first and second count fields Dec 19, 1996 Issued
Array ( [id] => 3815691 [patent_doc_number] => 05829025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction' [patent_app_type] => 1 [patent_app_number] => 8/767950 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6079 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829025.pdf [firstpage_image] =>[orig_patent_app_number] => 767950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767950
Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction Dec 16, 1996 Issued
Array ( [id] => 4044891 [patent_doc_number] => 05903916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation' [patent_app_type] => 1 [patent_app_number] => 8/766950 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4267 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903916.pdf [firstpage_image] =>[orig_patent_app_number] => 766950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766950
Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation Dec 15, 1996 Issued
Array ( [id] => 4040759 [patent_doc_number] => 05926836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Computer and associated method for restoring data backed up on archive media' [patent_app_type] => 1 [patent_app_number] => 8/753952 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4059 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926836.pdf [firstpage_image] =>[orig_patent_app_number] => 753952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753952
Computer and associated method for restoring data backed up on archive media Dec 2, 1996 Issued
Array ( [id] => 3814186 [patent_doc_number] => 05781918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Memory system and method for selecting a different number of data channels depending on bus size' [patent_app_type] => 1 [patent_app_number] => 8/758218 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 19016 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781918.pdf [firstpage_image] =>[orig_patent_app_number] => 758218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758218
Memory system and method for selecting a different number of data channels depending on bus size Nov 26, 1996 Issued
Array ( [id] => 4270017 [patent_doc_number] => 06223247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Disk shaped recording medium and drive apparatus utilizing logical block address conversion and start addresses which increase from inner and outer circumferential sides of the medium' [patent_app_type] => 1 [patent_app_number] => 8/750223 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 57 [patent_no_of_words] => 14484 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223247.pdf [firstpage_image] =>[orig_patent_app_number] => 750223 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/750223
Disk shaped recording medium and drive apparatus utilizing logical block address conversion and start addresses which increase from inner and outer circumferential sides of the medium Nov 25, 1996 Issued
Array ( [id] => 1505994 [patent_doc_number] => 06487644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'System and method for multiplexed data back-up to a storage tape and restore operations using client identification tags' [patent_app_type] => B1 [patent_app_number] => 08/755004 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4779 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487644.pdf [firstpage_image] =>[orig_patent_app_number] => 08755004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755004
System and method for multiplexed data back-up to a storage tape and restore operations using client identification tags Nov 21, 1996 Issued
Array ( [id] => 4010952 [patent_doc_number] => 05920882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Programmable circuit assembly and methods for high bandwidth data processing' [patent_app_type] => 1 [patent_app_number] => 8/752940 [patent_app_country] => US [patent_app_date] => 1996-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8552 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920882.pdf [firstpage_image] =>[orig_patent_app_number] => 752940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752940
Programmable circuit assembly and methods for high bandwidth data processing Nov 20, 1996 Issued
Array ( [id] => 4027082 [patent_doc_number] => 05890214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Dynamically upgradeable disk array chassis and method for dynamically upgrading a data storage system utilizing a selectively switchable shunt' [patent_app_type] => 1 [patent_app_number] => 8/748884 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6952 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890214.pdf [firstpage_image] =>[orig_patent_app_number] => 748884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748884
Dynamically upgradeable disk array chassis and method for dynamically upgrading a data storage system utilizing a selectively switchable shunt Nov 13, 1996 Issued
Array ( [id] => 1298111 [patent_doc_number] => 06631454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies' [patent_app_type] => B1 [patent_app_number] => 08/748862 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9098 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631454.pdf [firstpage_image] =>[orig_patent_app_number] => 08748862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748862
Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies Nov 12, 1996 Issued
Array ( [id] => 3805856 [patent_doc_number] => 05822769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Dual port random access memory matching circuit for versa module Europe bus (VMEbus)' [patent_app_type] => 1 [patent_app_number] => 8/742894 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2848 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822769.pdf [firstpage_image] =>[orig_patent_app_number] => 742894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742894
Dual port random access memory matching circuit for versa module Europe bus (VMEbus) Oct 31, 1996 Issued
Array ( [id] => 3955126 [patent_doc_number] => 05940850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'System and method for selectively enabling load-on-write of dynamic ROM data to RAM' [patent_app_type] => 1 [patent_app_number] => 8/742108 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2565 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940850.pdf [firstpage_image] =>[orig_patent_app_number] => 742108 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742108
System and method for selectively enabling load-on-write of dynamic ROM data to RAM Oct 30, 1996 Issued
Array ( [id] => 4133069 [patent_doc_number] => 06047352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure' [patent_app_type] => 1 [patent_app_number] => 8/739266 [patent_app_country] => US [patent_app_date] => 1996-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13459 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047352.pdf [firstpage_image] =>[orig_patent_app_number] => 739266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739266
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Oct 28, 1996 Issued
Array ( [id] => 3955452 [patent_doc_number] => 05940871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Computer system and method for selectively decompressing operating system ROM image code using a page fault' [patent_app_type] => 1 [patent_app_number] => 8/739228 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3590 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940871.pdf [firstpage_image] =>[orig_patent_app_number] => 739228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739228
Computer system and method for selectively decompressing operating system ROM image code using a page fault Oct 27, 1996 Issued
Array ( [id] => 3970487 [patent_doc_number] => 05991852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Cache ram using a secondary controller and switching circuit and improved chassis arrangement' [patent_app_type] => 1 [patent_app_number] => 8/738766 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3993 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991852.pdf [firstpage_image] =>[orig_patent_app_number] => 738766 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738766
Cache ram using a secondary controller and switching circuit and improved chassis arrangement Oct 27, 1996 Issued
Array ( [id] => 3798086 [patent_doc_number] => 05809526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Data processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operation' [patent_app_type] => 1 [patent_app_number] => 8/740368 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3696 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809526.pdf [firstpage_image] =>[orig_patent_app_number] => 740368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/740368
Data processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operation Oct 27, 1996 Issued
Array ( [id] => 4206695 [patent_doc_number] => 06131145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations' [patent_app_type] => 1 [patent_app_number] => 8/738912 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5028 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131145.pdf [firstpage_image] =>[orig_patent_app_number] => 738912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738912
Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations Oct 27, 1996 Issued
Array ( [id] => 3960238 [patent_doc_number] => 05930817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and system including operation information accessible by a system on a network utilizing a file access command of a host operating system' [patent_app_type] => 1 [patent_app_number] => 8/731968 [patent_app_country] => US [patent_app_date] => 1996-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 7673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930817.pdf [firstpage_image] =>[orig_patent_app_number] => 731968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731968
Method and system including operation information accessible by a system on a network utilizing a file access command of a host operating system Oct 22, 1996 Issued
Array ( [id] => 4040669 [patent_doc_number] => 05926830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Data processing system and method for maintaining coherency between high and low level caches using inclusive states' [patent_app_type] => 1 [patent_app_number] => 8/726948 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11286 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926830.pdf [firstpage_image] =>[orig_patent_app_number] => 726948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/726948
Data processing system and method for maintaining coherency between high and low level caches using inclusive states Oct 6, 1996 Issued
Array ( [id] => 4033709 [patent_doc_number] => 05963978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators' [patent_app_type] => 1 [patent_app_number] => 8/726944 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11199 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963978.pdf [firstpage_image] =>[orig_patent_app_number] => 726944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/726944
High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators Oct 6, 1996 Issued
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