Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4225742 [patent_doc_number] => 06029226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command' [patent_app_type] => 1 [patent_app_number] => 8/724522 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4157 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029226.pdf [firstpage_image] =>[orig_patent_app_number] => 724522 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724522
Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command Sep 29, 1996 Issued
Array ( [id] => 4085325 [patent_doc_number] => 06009504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Apparatus and method for storing data associated with multiple addresses in a storage element using a base address and a mask' [patent_app_type] => 1 [patent_app_number] => 8/726047 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009504.pdf [firstpage_image] =>[orig_patent_app_number] => 726047 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/726047
Apparatus and method for storing data associated with multiple addresses in a storage element using a base address and a mask Sep 26, 1996 Issued
Array ( [id] => 3757497 [patent_doc_number] => 05787381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Control apparatus for automobile engine including microcomputer which may be programmed after mounting on a circuit board' [patent_app_type] => 1 [patent_app_number] => 8/721324 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6345 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787381.pdf [firstpage_image] =>[orig_patent_app_number] => 721324 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721324
Control apparatus for automobile engine including microcomputer which may be programmed after mounting on a circuit board Sep 25, 1996 Issued
Array ( [id] => 4309477 [patent_doc_number] => 06198687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations' [patent_app_type] => 1 [patent_app_number] => 8/716884 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 59 [patent_no_of_words] => 4373 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198687.pdf [firstpage_image] =>[orig_patent_app_number] => 716884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/716884
Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations Sep 19, 1996 Issued
Array ( [id] => 3961679 [patent_doc_number] => 05974517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method and system for mounting a system partition as a logical drive while an operating system is operational by modifying a partition table' [patent_app_type] => 1 [patent_app_number] => 8/710360 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974517.pdf [firstpage_image] =>[orig_patent_app_number] => 710360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710360
Method and system for mounting a system partition as a logical drive while an operating system is operational by modifying a partition table Sep 16, 1996 Issued
Array ( [id] => 3660315 [patent_doc_number] => 05640529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method and system for performing clean-up of a solid state disk during host command execution' [patent_app_type] => 1 [patent_app_number] => 8/714504 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7564 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640529.pdf [firstpage_image] =>[orig_patent_app_number] => 714504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714504
Method and system for performing clean-up of a solid state disk during host command execution Sep 15, 1996 Issued
Array ( [id] => 4073076 [patent_doc_number] => 05864877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Apparatus and method for fast forwarding of table index (TI) bit for descriptor table selection' [patent_app_type] => 1 [patent_app_number] => 8/712203 [patent_app_country] => US [patent_app_date] => 1996-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6182 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864877.pdf [firstpage_image] =>[orig_patent_app_number] => 712203 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712203
Apparatus and method for fast forwarding of table index (TI) bit for descriptor table selection Sep 10, 1996 Issued
Array ( [id] => 4059734 [patent_doc_number] => 05875475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Continuous data server apparatus and method for controlling continuous data server' [patent_app_type] => 1 [patent_app_number] => 8/707940 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 7092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875475.pdf [firstpage_image] =>[orig_patent_app_number] => 707940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707940
Continuous data server apparatus and method for controlling continuous data server Sep 9, 1996 Issued
90/004357 MEMORY MODULE ARRANGED FOR DATA AND PARITY BITS Sep 5, 1996 Issued
90/004358 MEMORY MODULE ARRANGED FOR DATA AND PARITY BITS Sep 5, 1996 Issued
Array ( [id] => 3997387 [patent_doc_number] => 05911152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Computer system and method for storing data in a buffer which crosses page boundaries utilizing beginning and ending buffer pointers' [patent_app_type] => 1 [patent_app_number] => 8/711357 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9098 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911152.pdf [firstpage_image] =>[orig_patent_app_number] => 711357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711357
Computer system and method for storing data in a buffer which crosses page boundaries utilizing beginning and ending buffer pointers Sep 4, 1996 Issued
Array ( [id] => 3758616 [patent_doc_number] => 05787458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Content addressable memory of a simple construction capable of retrieving a variable word length data' [patent_app_type] => 1 [patent_app_number] => 8/706470 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6901 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787458.pdf [firstpage_image] =>[orig_patent_app_number] => 706470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/706470
Content addressable memory of a simple construction capable of retrieving a variable word length data Sep 2, 1996 Issued
Array ( [id] => 3960197 [patent_doc_number] => 05930814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Computer system and method for synthesizing a filter circuit for filtering out addresses greater than a maximum address' [patent_app_type] => 1 [patent_app_number] => 8/697968 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3894 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930814.pdf [firstpage_image] =>[orig_patent_app_number] => 697968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/697968
Computer system and method for synthesizing a filter circuit for filtering out addresses greater than a maximum address Sep 2, 1996 Issued
Array ( [id] => 3858386 [patent_doc_number] => 05719812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Semiconductor memory including bit line reset circuitry and a pulse generator having output delay time dependent on type of transition in an input signal' [patent_app_type] => 1 [patent_app_number] => 8/718014 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 5830 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719812.pdf [firstpage_image] =>[orig_patent_app_number] => 718014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718014
Semiconductor memory including bit line reset circuitry and a pulse generator having output delay time dependent on type of transition in an input signal Sep 2, 1996 Issued
Array ( [id] => 3798505 [patent_doc_number] => 05809552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions' [patent_app_type] => 1 [patent_app_number] => 8/705562 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 132 [patent_figures_cnt] => 145 [patent_no_of_words] => 48147 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809552.pdf [firstpage_image] =>[orig_patent_app_number] => 705562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705562
Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions Aug 28, 1996 Issued
Array ( [id] => 4126764 [patent_doc_number] => 06058459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Video/audio decompression/compression device including an arbiter and method for accessing a shared memory' [patent_app_type] => 1 [patent_app_number] => 8/702910 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058459.pdf [firstpage_image] =>[orig_patent_app_number] => 702910 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702910
Video/audio decompression/compression device including an arbiter and method for accessing a shared memory Aug 25, 1996 Issued
Array ( [id] => 4011112 [patent_doc_number] => 05920892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests' [patent_app_type] => 1 [patent_app_number] => 8/703118 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5838 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920892.pdf [firstpage_image] =>[orig_patent_app_number] => 703118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703118
Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests Aug 25, 1996 Issued
Array ( [id] => 4133213 [patent_doc_number] => 06047361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Memory control device, with a common synchronous interface coupled thereto, for accessing asynchronous memory devices and different synchronous devices' [patent_app_type] => 1 [patent_app_number] => 8/701228 [patent_app_country] => US [patent_app_date] => 1996-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5509 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047361.pdf [firstpage_image] =>[orig_patent_app_number] => 701228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701228
Memory control device, with a common synchronous interface coupled thereto, for accessing asynchronous memory devices and different synchronous devices Aug 20, 1996 Issued
Array ( [id] => 4058958 [patent_doc_number] => 05909693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'System and method for striping data across multiple disks for continuous data streaming and increased bus utilization' [patent_app_type] => 1 [patent_app_number] => 8/694432 [patent_app_country] => US [patent_app_date] => 1996-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4333 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909693.pdf [firstpage_image] =>[orig_patent_app_number] => 694432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694432
System and method for striping data across multiple disks for continuous data streaming and increased bus utilization Aug 11, 1996 Issued
Array ( [id] => 3954853 [patent_doc_number] => 05900015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'System and method for maintaining cache coherency using path directories' [patent_app_type] => 1 [patent_app_number] => 8/694894 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5201 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900015.pdf [firstpage_image] =>[orig_patent_app_number] => 694894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694894
System and method for maintaining cache coherency using path directories Aug 8, 1996 Issued
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