Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4011182 [patent_doc_number] => 05920897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Apparatus and method for providing multiple channel clock-data alignment' [patent_app_type] => 1 [patent_app_number] => 8/693760 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7656 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920897.pdf [firstpage_image] =>[orig_patent_app_number] => 693760 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/693760
Apparatus and method for providing multiple channel clock-data alignment Aug 6, 1996 Issued
Array ( [id] => 3955326 [patent_doc_number] => 05940863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Apparatus for de-rotating and de-interleaving data including plural memory devices and plural modulo memory address generators' [patent_app_type] => 1 [patent_app_number] => 8/687866 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8353 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940863.pdf [firstpage_image] =>[orig_patent_app_number] => 687866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/687866
Apparatus for de-rotating and de-interleaving data including plural memory devices and plural modulo memory address generators Jul 25, 1996 Issued
Array ( [id] => 4059356 [patent_doc_number] => 05875449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Computer connection available data wireless apparatus with clock signal frequency variable function' [patent_app_type] => 1 [patent_app_number] => 8/681359 [patent_app_country] => US [patent_app_date] => 1996-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875449.pdf [firstpage_image] =>[orig_patent_app_number] => 681359 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681359
Computer connection available data wireless apparatus with clock signal frequency variable function Jul 22, 1996 Issued
Array ( [id] => 3833575 [patent_doc_number] => 05813043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method and system including memory patching utilizing a transmission control signal and circuit' [patent_app_type] => 1 [patent_app_number] => 8/678898 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4497 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813043.pdf [firstpage_image] =>[orig_patent_app_number] => 678898 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678898
Method and system including memory patching utilizing a transmission control signal and circuit Jul 11, 1996 Issued
Array ( [id] => 4259835 [patent_doc_number] => 06092157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Processing method, apparatus and system for memory management using shared memories with common data areas' [patent_app_type] => 1 [patent_app_number] => 8/675414 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5681 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092157.pdf [firstpage_image] =>[orig_patent_app_number] => 675414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675414
Processing method, apparatus and system for memory management using shared memories with common data areas Jul 1, 1996 Issued
Array ( [id] => 3843556 [patent_doc_number] => 05784709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Translating buffer and method for translating addresses utilizing invalid and don\'t care states' [patent_app_type] => 1 [patent_app_number] => 8/674470 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8660 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784709.pdf [firstpage_image] =>[orig_patent_app_number] => 674470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674470
Translating buffer and method for translating addresses utilizing invalid and don't care states Jul 1, 1996 Issued
08/673863 CONTENT ADDRESSABLE MEMORY HAVING MEMORY CELLS STORING DON'T CARE STATES FOR ADDRESS TRANSLATION Jul 1, 1996 Abandoned
Array ( [id] => 4138925 [patent_doc_number] => 06073224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Network interface circuit with replacement circuitry and method for segregating memory in an address translation unit with locked and unlocked regions' [patent_app_type] => 1 [patent_app_number] => 8/673050 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6356 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073224.pdf [firstpage_image] =>[orig_patent_app_number] => 673050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673050
Network interface circuit with replacement circuitry and method for segregating memory in an address translation unit with locked and unlocked regions Jun 30, 1996 Issued
Array ( [id] => 3908275 [patent_doc_number] => 05778432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register' [patent_app_type] => 1 [patent_app_number] => 8/674050 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3963 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778432.pdf [firstpage_image] =>[orig_patent_app_number] => 674050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674050
Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register Jun 30, 1996 Issued
Array ( [id] => 3955285 [patent_doc_number] => 05940860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains' [patent_app_type] => 1 [patent_app_number] => 8/677012 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9590 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940860.pdf [firstpage_image] =>[orig_patent_app_number] => 677012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677012
Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains Jun 30, 1996 Issued
Array ( [id] => 3978321 [patent_doc_number] => 05937436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Network interface circuit including an address translation unit and flush control circuit and method for checking for invalid address translations' [patent_app_type] => 1 [patent_app_number] => 8/674095 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6367 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937436.pdf [firstpage_image] =>[orig_patent_app_number] => 674095 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674095
Network interface circuit including an address translation unit and flush control circuit and method for checking for invalid address translations Jun 30, 1996 Issued
Array ( [id] => 4402172 [patent_doc_number] => 06279078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Apparatus and method for synchronizing a cache mode in a dual controller, dual cache memory system operating in a plurality of cache modes' [patent_app_type] => 1 [patent_app_number] => 8/668512 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3950 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279078.pdf [firstpage_image] =>[orig_patent_app_number] => 668512 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668512
Apparatus and method for synchronizing a cache mode in a dual controller, dual cache memory system operating in a plurality of cache modes Jun 27, 1996 Issued
Array ( [id] => 4211506 [patent_doc_number] => 06044445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Data transfer method and memory management system utilizing access control information to change mapping between physical and virtual pages for improved data transfer efficiency' [patent_app_type] => 1 [patent_app_number] => 8/672370 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 15119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044445.pdf [firstpage_image] =>[orig_patent_app_number] => 672370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672370
Data transfer method and memory management system utilizing access control information to change mapping between physical and virtual pages for improved data transfer efficiency Jun 27, 1996 Issued
Array ( [id] => 3954930 [patent_doc_number] => 05900020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency' [patent_app_type] => 1 [patent_app_number] => 8/678372 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7315 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900020.pdf [firstpage_image] =>[orig_patent_app_number] => 678372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678372
Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency Jun 26, 1996 Issued
Array ( [id] => 3902696 [patent_doc_number] => 05724547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'LRU pointer updating in a controller for two-way set associative cache' [patent_app_type] => 1 [patent_app_number] => 8/671446 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724547.pdf [firstpage_image] =>[orig_patent_app_number] => 671446 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671446
LRU pointer updating in a controller for two-way set associative cache Jun 26, 1996 Issued
Array ( [id] => 3797879 [patent_doc_number] => 05809515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Semiconductor storage device in which instructions are sequentially fed to a plurality of flash memories to continuously write and erase data' [patent_app_type] => 1 [patent_app_number] => 8/669914 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6330 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809515.pdf [firstpage_image] =>[orig_patent_app_number] => 669914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/669914
Semiconductor storage device in which instructions are sequentially fed to a plurality of flash memories to continuously write and erase data Jun 24, 1996 Issued
Array ( [id] => 3782131 [patent_doc_number] => 05845326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Computer system and method for obtaining memory check points and recovering from faults using the checkpoints and cache flush operations' [patent_app_type] => 1 [patent_app_number] => 8/665544 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3400 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845326.pdf [firstpage_image] =>[orig_patent_app_number] => 665544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665544
Computer system and method for obtaining memory check points and recovering from faults using the checkpoints and cache flush operations Jun 17, 1996 Issued
08/659482 APPARATUS AND METHOD FOR MANAGING THE CACHING OF DATA AT NETWORK SITES USING DIFFERENT CACHE MANAGEMENT SYSTEMS Jun 5, 1996 Abandoned
Array ( [id] => 3913339 [patent_doc_number] => 05835947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses' [patent_app_type] => 1 [patent_app_number] => 8/656402 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3912 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835947.pdf [firstpage_image] =>[orig_patent_app_number] => 656402 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656402
Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses May 30, 1996 Issued
Array ( [id] => 4422598 [patent_doc_number] => 06173379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle' [patent_app_type] => 1 [patent_app_number] => 8/645653 [patent_app_country] => US [patent_app_date] => 1996-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4158 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173379.pdf [firstpage_image] =>[orig_patent_app_number] => 645653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645653
Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle May 13, 1996 Issued
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