Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1443887 [patent_doc_number] => 06336161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Computer configuration system and method with state and restoration from non-volatile semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 08/572972 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4414 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336161.pdf [firstpage_image] =>[orig_patent_app_number] => 08572972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572972
Computer configuration system and method with state and restoration from non-volatile semiconductor memory Dec 14, 1995 Issued
Array ( [id] => 3796365 [patent_doc_number] => 05758118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Methods and data storage devices for RAID expansion by on-line addition of new DASDs' [patent_app_type] => 1 [patent_app_number] => 8/569932 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6050 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758118.pdf [firstpage_image] =>[orig_patent_app_number] => 569932 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/569932
Methods and data storage devices for RAID expansion by on-line addition of new DASDs Dec 7, 1995 Issued
Array ( [id] => 4273588 [patent_doc_number] => 06209067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Computer system controller and method with processor write posting hold off on PCI master memory request' [patent_app_type] => 1 [patent_app_number] => 8/566514 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 24681 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209067.pdf [firstpage_image] =>[orig_patent_app_number] => 566514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566514
Computer system controller and method with processor write posting hold off on PCI master memory request Dec 3, 1995 Issued
Array ( [id] => 3852990 [patent_doc_number] => 05761694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Multi-bank memory system and method having addresses switched between the row and column decoders in different banks' [patent_app_type] => 1 [patent_app_number] => 8/565388 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4906 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761694.pdf [firstpage_image] =>[orig_patent_app_number] => 565388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565388
Multi-bank memory system and method having addresses switched between the row and column decoders in different banks Nov 29, 1995 Issued
Array ( [id] => 3621193 [patent_doc_number] => 05590298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method of restoring and updating records in a disk cache system during disk drive idle time using start and end addresses' [patent_app_type] => 1 [patent_app_number] => 8/553822 [patent_app_country] => US [patent_app_date] => 1995-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4694 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590298.pdf [firstpage_image] =>[orig_patent_app_number] => 553822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/553822
Method of restoring and updating records in a disk cache system during disk drive idle time using start and end addresses Nov 5, 1995 Issued
Array ( [id] => 3828794 [patent_doc_number] => 05771367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Storage controller and method for improved failure recovery using cross-coupled cache memories and nonvolatile stores' [patent_app_type] => 1 [patent_app_number] => 8/550184 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3847 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771367.pdf [firstpage_image] =>[orig_patent_app_number] => 550184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550184
Storage controller and method for improved failure recovery using cross-coupled cache memories and nonvolatile stores Oct 29, 1995 Issued
Array ( [id] => 3860225 [patent_doc_number] => 05848435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Address protection circuit and method for preventing access to unauthorized address rangers' [patent_app_type] => 1 [patent_app_number] => 8/551928 [patent_app_country] => US [patent_app_date] => 1995-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4115 [patent_no_of_claims] => 106 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848435.pdf [firstpage_image] =>[orig_patent_app_number] => 551928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551928
Address protection circuit and method for preventing access to unauthorized address rangers Oct 22, 1995 Issued
Array ( [id] => 3762005 [patent_doc_number] => 05802343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method of prioritizing subsequently received program and erase commands during a block operation for a nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/543320 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9045 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802343.pdf [firstpage_image] =>[orig_patent_app_number] => 543320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543320
Method of prioritizing subsequently received program and erase commands during a block operation for a nonvolatile semiconductor memory Oct 15, 1995 Issued
Array ( [id] => 3798345 [patent_doc_number] => 05809541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Methods for prioritizing erase and program commands in a nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/543710 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9046 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809541.pdf [firstpage_image] =>[orig_patent_app_number] => 543710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543710
Methods for prioritizing erase and program commands in a nonvolatile semiconductor memory device Oct 15, 1995 Issued
Array ( [id] => 3938111 [patent_doc_number] => 05915261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Toy electronic information storage medium' [patent_app_type] => 1 [patent_app_number] => 8/542807 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2947 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915261.pdf [firstpage_image] =>[orig_patent_app_number] => 542807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542807
Toy electronic information storage medium Oct 12, 1995 Issued
08/539305 MEMORY SYSTEM AND METHOD OF SELECTING A DIFFERENT NUMBER OF DATA CHANNELS DEPENDING ON BUS WIDTH AND MEMORY BANK CONFIGURATION Oct 2, 1995 Abandoned
08/538348 DYNAMICALLY CONFIGURABLE MEMORY SYSTEM HAVING A PROGRAMMABLE CONTROLLER INCLUDING A FREQUENCY MULTIPLIER TO MAINTAIN MEMORY TIMING RESOLUTION FOR DIFFERENT BUS SPEEDS Oct 2, 1995 Abandoned
Array ( [id] => 4071549 [patent_doc_number] => 05933845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Flash memory management method including shifting or copying data to other blocks to optimize storage space and allow entire blocks to be erased' [patent_app_type] => 1 [patent_app_number] => 8/536852 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3960 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933845.pdf [firstpage_image] =>[orig_patent_app_number] => 536852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536852
Flash memory management method including shifting or copying data to other blocks to optimize storage space and allow entire blocks to be erased Sep 28, 1995 Issued
Array ( [id] => 3660286 [patent_doc_number] => 05640527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states' [patent_app_type] => 1 [patent_app_number] => 8/521259 [patent_app_country] => US [patent_app_date] => 1995-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4330 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640527.pdf [firstpage_image] =>[orig_patent_app_number] => 521259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521259
Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states Aug 29, 1995 Issued
Array ( [id] => 3954509 [patent_doc_number] => 05873114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles' [patent_app_type] => 1 [patent_app_number] => 8/516832 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6918 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873114.pdf [firstpage_image] =>[orig_patent_app_number] => 516832 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516832
Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles Aug 17, 1995 Issued
Array ( [id] => 4059453 [patent_doc_number] => 05875456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Storage device array and methods for striping and unstriping data and for adding and removing disks online to/from a raid storage array' [patent_app_type] => 1 [patent_app_number] => 8/516232 [patent_app_country] => US [patent_app_date] => 1995-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 13610 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875456.pdf [firstpage_image] =>[orig_patent_app_number] => 516232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516232
Storage device array and methods for striping and unstriping data and for adding and removing disks online to/from a raid storage array Aug 16, 1995 Issued
Array ( [id] => 3566148 [patent_doc_number] => 05574881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'High capacity data storage method and system using independently controlled heads and circuitry for monitoring access frequency of data records' [patent_app_type] => 1 [patent_app_number] => 8/511779 [patent_app_country] => US [patent_app_date] => 1995-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8334 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574881.pdf [firstpage_image] =>[orig_patent_app_number] => 511779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/511779
High capacity data storage method and system using independently controlled heads and circuitry for monitoring access frequency of data records Aug 9, 1995 Issued
Array ( [id] => 3716490 [patent_doc_number] => 05675763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Cache memory system and method for selectively removing stale aliased entries' [patent_app_type] => 1 [patent_app_number] => 8/514350 [patent_app_country] => US [patent_app_date] => 1995-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3741 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675763.pdf [firstpage_image] =>[orig_patent_app_number] => 514350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/514350
Cache memory system and method for selectively removing stale aliased entries Aug 3, 1995 Issued
08/495373 SEMICONDUCTOR MEMORY INCLUDING A CONTROL CIRCUIT HAVING OUTPUT DELAY TIME DEPENDENT ON TYPE OF CHANGE IN AN INPUT SIGNAL Jun 27, 1995 Abandoned
Array ( [id] => 3918607 [patent_doc_number] => 05751999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Processor and data memory for outputting and receiving data on different buses for storage in the same location' [patent_app_type] => 1 [patent_app_number] => 8/492702 [patent_app_country] => US [patent_app_date] => 1995-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3756 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751999.pdf [firstpage_image] =>[orig_patent_app_number] => 492702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/492702
Processor and data memory for outputting and receiving data on different buses for storage in the same location Jun 19, 1995 Issued
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