Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1484968 [patent_doc_number] => 06453388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Computer system having a bus interface unit for prefetching data from system memory' [patent_app_type] => B1 [patent_app_number] => 08/438473 [patent_app_country] => US [patent_app_date] => 1995-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4309 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453388.pdf [firstpage_image] =>[orig_patent_app_number] => 08438473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438473
Computer system having a bus interface unit for prefetching data from system memory May 9, 1995 Issued
08/437643 CACHE MEMORY SYSTEM AND METHOD FOR AUTOMATICALLY LOCKING CACHE ENTRIES TO PREVENT SELECTED MEMORY ITEMS FROM BEING REPLACED May 8, 1995 Abandoned
Array ( [id] => 3596649 [patent_doc_number] => 05553024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Semiconductor memory utilizing RAS and CAS signals to control the latching of first and second read or write data' [patent_app_type] => 1 [patent_app_number] => 8/419769 [patent_app_country] => US [patent_app_date] => 1995-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3828 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553024.pdf [firstpage_image] =>[orig_patent_app_number] => 419769 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/419769
Semiconductor memory utilizing RAS and CAS signals to control the latching of first and second read or write data Apr 9, 1995 Issued
Array ( [id] => 3805891 [patent_doc_number] => 05737746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Computer system including an apparatus for reducing power consumption in an on-chip tag static RAM' [patent_app_type] => 1 [patent_app_number] => 8/415600 [patent_app_country] => US [patent_app_date] => 1995-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4959 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737746.pdf [firstpage_image] =>[orig_patent_app_number] => 415600 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/415600
Computer system including an apparatus for reducing power consumption in an on-chip tag static RAM Apr 2, 1995 Issued
Array ( [id] => 3735813 [patent_doc_number] => 05701426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio' [patent_app_type] => 1 [patent_app_number] => 8/414602 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4558 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701426.pdf [firstpage_image] =>[orig_patent_app_number] => 414602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/414602
Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio Mar 30, 1995 Issued
Array ( [id] => 3833480 [patent_doc_number] => 05813037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data lines and a capacitance isolation mechanism' [patent_app_type] => 1 [patent_app_number] => 8/413962 [patent_app_country] => US [patent_app_date] => 1995-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5348 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813037.pdf [firstpage_image] =>[orig_patent_app_number] => 413962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/413962
Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data lines and a capacitance isolation mechanism Mar 29, 1995 Issued
Array ( [id] => 3503308 [patent_doc_number] => 05561783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Dynamic cache coherency method and apparatus using both write-back and write-through operations' [patent_app_type] => 1 [patent_app_number] => 8/409884 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4902 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561783.pdf [firstpage_image] =>[orig_patent_app_number] => 409884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409884
Dynamic cache coherency method and apparatus using both write-back and write-through operations Mar 21, 1995 Issued
Array ( [id] => 3805920 [patent_doc_number] => 05737748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory' [patent_app_type] => 1 [patent_app_number] => 8/404702 [patent_app_country] => US [patent_app_date] => 1995-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 33858 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737748.pdf [firstpage_image] =>[orig_patent_app_number] => 404702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/404702
Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory Mar 14, 1995 Issued
Array ( [id] => 3898456 [patent_doc_number] => 05765218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Address generating circuit for generating addresses separated by a prescribed step value in circular addressing' [patent_app_type] => 1 [patent_app_number] => 8/402224 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 13512 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765218.pdf [firstpage_image] =>[orig_patent_app_number] => 402224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/402224
Address generating circuit for generating addresses separated by a prescribed step value in circular addressing Mar 9, 1995 Issued
Array ( [id] => 3700953 [patent_doc_number] => 05644747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Page mode access memory controller including plural address latches and a comparator' [patent_app_type] => 1 [patent_app_number] => 8/398442 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5004 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644747.pdf [firstpage_image] =>[orig_patent_app_number] => 398442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/398442
Page mode access memory controller including plural address latches and a comparator Mar 2, 1995 Issued
Array ( [id] => 3518999 [patent_doc_number] => 05587952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Dynamic random access memory including read preamplifiers activated before rewrite amplifiers' [patent_app_type] => 1 [patent_app_number] => 8/391537 [patent_app_country] => US [patent_app_date] => 1995-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10267 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587952.pdf [firstpage_image] =>[orig_patent_app_number] => 391537 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/391537
Dynamic random access memory including read preamplifiers activated before rewrite amplifiers Feb 20, 1995 Issued
Array ( [id] => 3697148 [patent_doc_number] => 05696715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Semiconductor memory device having bipolar and field effect transistors and an improved coupling arrangement for logic units or logic blocks' [patent_app_type] => 1 [patent_app_number] => 8/387628 [patent_app_country] => US [patent_app_date] => 1995-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 5480 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696715.pdf [firstpage_image] =>[orig_patent_app_number] => 387628 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/387628
Semiconductor memory device having bipolar and field effect transistors and an improved coupling arrangement for logic units or logic blocks Feb 12, 1995 Issued
Array ( [id] => 3501600 [patent_doc_number] => 05471605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Apparatus for updating a multi-way set associative cache memory status array' [patent_app_type] => 1 [patent_app_number] => 8/384622 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3542 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471605.pdf [firstpage_image] =>[orig_patent_app_number] => 384622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/384622
Apparatus for updating a multi-way set associative cache memory status array Feb 5, 1995 Issued
Array ( [id] => 3659971 [patent_doc_number] => 05630094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions' [patent_app_type] => 1 [patent_app_number] => 8/375972 [patent_app_country] => US [patent_app_date] => 1995-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2789 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630094.pdf [firstpage_image] =>[orig_patent_app_number] => 375972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375972
Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions Jan 19, 1995 Issued
Array ( [id] => 3603678 [patent_doc_number] => 05586293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Real time cache implemented by on-chip memory having standard and cache operating modes' [patent_app_type] => 1 [patent_app_number] => 8/372728 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4937 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586293.pdf [firstpage_image] =>[orig_patent_app_number] => 372728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/372728
Real time cache implemented by on-chip memory having standard and cache operating modes Jan 16, 1995 Issued
Array ( [id] => 3751119 [patent_doc_number] => 05699549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Memory card having a card management information area for improved format capability and recording, reproducing, and erasing methods therefor' [patent_app_type] => 1 [patent_app_number] => 8/366915 [patent_app_country] => US [patent_app_date] => 1994-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6622 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699549.pdf [firstpage_image] =>[orig_patent_app_number] => 366915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/366915
Memory card having a card management information area for improved format capability and recording, reproducing, and erasing methods therefor Dec 29, 1994 Issued
Array ( [id] => 3669839 [patent_doc_number] => 05659705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Serial access memory cartridge for programmable logic controller' [patent_app_type] => 1 [patent_app_number] => 8/365642 [patent_app_country] => US [patent_app_date] => 1994-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11591 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659705.pdf [firstpage_image] =>[orig_patent_app_number] => 365642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/365642
Serial access memory cartridge for programmable logic controller Dec 28, 1994 Issued
Array ( [id] => 3527061 [patent_doc_number] => 05506803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Apparatus and method for minimizing verify time in a semiconductor memory by constantly charging n-well capacitance' [patent_app_type] => 1 [patent_app_number] => 8/361872 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5095 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506803.pdf [firstpage_image] =>[orig_patent_app_number] => 361872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361872
Apparatus and method for minimizing verify time in a semiconductor memory by constantly charging n-well capacitance Dec 21, 1994 Issued
Array ( [id] => 3530473 [patent_doc_number] => 05577229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Computer system and method for pipelined transfer of data between modules utilizing a shared memory and a pipeline having a plurality of registers' [patent_app_type] => 1 [patent_app_number] => 8/359112 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7226 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577229.pdf [firstpage_image] =>[orig_patent_app_number] => 359112 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359112
Computer system and method for pipelined transfer of data between modules utilizing a shared memory and a pipeline having a plurality of registers Dec 18, 1994 Issued
Array ( [id] => 3636634 [patent_doc_number] => 05603009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM' [patent_app_type] => 1 [patent_app_number] => 8/356046 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 93 [patent_figures_cnt] => 116 [patent_no_of_words] => 44673 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603009.pdf [firstpage_image] =>[orig_patent_app_number] => 356046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/356046
Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM Dec 13, 1994 Issued
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