| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus'
[patent_app_type] => 1
[patent_app_number] => 8/353165
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/353165 | System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus | Dec 8, 1994 | Issued |
Array
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[patent_doc_number] => 05668968
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[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Two-level virtual/real set associative cache system and method with improved synonym detection'
[patent_app_type] => 1
[patent_app_number] => 8/345802
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[firstpage_image] =>[orig_patent_app_number] => 345802
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/345802 | Two-level virtual/real set associative cache system and method with improved synonym detection | Nov 21, 1994 | Issued |
Array
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[id] => 3605926
[patent_doc_number] => 05522060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Multiprocessor memory managing system and method for executing sequentially renewed instructions by locking and alternately reading slave memories'
[patent_app_type] => 1
[patent_app_number] => 8/331291
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 331291
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/331291 | Multiprocessor memory managing system and method for executing sequentially renewed instructions by locking and alternately reading slave memories | Oct 27, 1994 | Issued |
Array
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[patent_doc_number] => 05673414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device'
[patent_app_type] => 1
[patent_app_number] => 8/327136
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/327136 | Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device | Oct 20, 1994 | Issued |
Array
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[id] => 3672636
[patent_doc_number] => 05592644
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[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Ferroelectric storage device emulating a rotating disk drive unit in a computer system and having an optical data interface'
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Array
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Array
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[patent_issue_date] => 1997-01-07
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Array
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[id] => 3701781
[patent_doc_number] => 05604881
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'Ferroelectric storage device emulating a rotating disk drive unit in a computer system and having a multiplexed optical data interface'
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Array
(
[id] => 3672663
[patent_doc_number] => 05592646
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[patent_kind] => NA
[patent_issue_date] => 1997-01-07
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[patent_app_number] => 8/326662
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Array
(
[id] => 3672650
[patent_doc_number] => 05592645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Ferroelectric storage device emulating a rotating disk drive unit in a computer system and having a frequency modulated (FM) data interface'
[patent_app_type] => 1
[patent_app_number] => 8/326661
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Array
(
[id] => 3504708
[patent_doc_number] => 05508957
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through'
[patent_app_type] => 1
[patent_app_number] => 8/312072
[patent_app_country] => US
[patent_app_date] => 1994-09-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/312072 | Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through | Sep 25, 1994 | Issued |
| 08/305572 | METHOD OF PRE CACHING OR PRE-FETCHING DATA UTILIZING THREAD LISTS AND MULTIMEDIA EDITING SYSTEM USING SUCH PRE-CACHING | Sep 13, 1994 | Abandoned |
Array
(
[id] => 3435187
[patent_doc_number] => 05459851
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[patent_kind] => NA
[patent_issue_date] => 1995-10-17
[patent_title] => 'Dual-port memory with selective read data output prohibition'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298083 | Dual-port memory with selective read data output prohibition | Aug 30, 1994 | Issued |
| 08/287704 | METHOD AND APPARATUS FOR PREFETCHING DATA FROM SYSTEM MEMORY TO A CONTROL PROCESSING UNIT | Aug 8, 1994 | Abandoned |
Array
(
[id] => 3425161
[patent_doc_number] => 05444858
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[patent_kind] => NA
[patent_issue_date] => 1995-08-22
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[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/276877 | Computer systems and methods for pipelined transfer of data between modules | Jul 17, 1994 | Issued |
Array
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[id] => 3428125
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[patent_kind] => NA
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[patent_title] => 'Method and apparatus for rapid data copying using reassigned backing pages'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/276512 | Method and apparatus for rapid data copying using reassigned backing pages | Jul 14, 1994 | Issued |
Array
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[patent_kind] => NA
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Array
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[patent_kind] => NA
[patent_issue_date] => 2001-04-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/262161 | Synchronous dynamic random access memory and data processing system using an address select signal | Jun 16, 1994 | Issued |
Array
(
[id] => 3922719
[patent_doc_number] => 05752256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Disk array apparatus and method for dividing and reading/writing partial data across a plurality of drive groups utilizing parallel processing'
[patent_app_type] => 1
[patent_app_number] => 8/250446
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/250446 | Disk array apparatus and method for dividing and reading/writing partial data across a plurality of drive groups utilizing parallel processing | May 26, 1994 | Issued |
| 08/245805 | LRU POINTER UPDATING IN A CONTROLLER FOR TWO-WAY SET ASSOCIATIVE CACHE | May 16, 1994 | Abandoned |