Danielle Jackson

Array ( [id] => 3437984 [patent_doc_number] => 05404489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'System and method for minimizing cache interruptions by inhibiting snoop cycles if access is to an exclusive page' [patent_app_type] => 1 [patent_app_number] => 8/236011 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5622 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404489.pdf [firstpage_image] =>[orig_patent_app_number] => 236011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3474284 [patent_doc_number] => 05469558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Dynamically reconfigurable memory system with programmable controller and FIFO buffered data channels' [patent_app_type] => 1 [patent_app_number] => 8/228927 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 18969 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469558.pdf [firstpage_image] =>[orig_patent_app_number] => 228927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3701139 [patent_doc_number] => 05692148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method and apparatus for improving system memory cost/performance using extended data out (EDO)DRAM and split column addresses' [patent_app_type] => 1 [patent_app_number] => 8/225522 [patent_app_country] => US [patent_app_date] => 1994-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2970 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692148.pdf [firstpage_image] =>[orig_patent_app_number] => 225522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657776 [patent_doc_number] => 05638317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Hierarchical DRAM array with grouped I/O lines and high speed sensing circuit' [patent_app_type] => 1 [patent_app_number] => 8/222507 [patent_app_country] => US [patent_app_date] => 1994-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4348 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638317.pdf [firstpage_image] =>[orig_patent_app_number] => 222507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463178 [patent_doc_number] => 05379264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Semiconductor memory device capable of multidirection data access' [patent_app_type] => 1 [patent_app_number] => 8/214161 [patent_app_country] => US [patent_app_date] => 1994-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 72 [patent_no_of_words] => 10198 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379264.pdf [firstpage_image] =>[orig_patent_app_number] => 214161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3465306 [patent_doc_number] => 05379401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Flash memory card including circuitry for selectively providing masked and unmasked ready/busy output signals' [patent_app_type] => 1 [patent_app_number] => 8/198134 [patent_app_country] => US [patent_app_date] => 1994-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 20208 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379401.pdf [firstpage_image] =>[orig_patent_app_number] => 198134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3456902 [patent_doc_number] => 05388248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Flash memory card including plural flash memories and circuitry for selectively outputting ready/busy signals in different operating modes' [patent_app_type] => 1 [patent_app_number] => 8/198789 [patent_app_country] => US [patent_app_date] => 1994-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 20156 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388248.pdf [firstpage_image] =>[orig_patent_app_number] => 198789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544480 [patent_doc_number] => 05584023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Computer system including a transparent and secure file transform mechanism' [patent_app_type] => 1 [patent_app_number] => 8/175192 [patent_app_country] => US [patent_app_date] => 1993-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9593 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584023.pdf [firstpage_image] =>[orig_patent_app_number] => 175192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622797 [patent_doc_number] => 05510934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Memory system including local and global caches for storing floating point and integer data' [patent_app_type] => 1 [patent_app_number] => 8/168832 [patent_app_country] => US [patent_app_date] => 1993-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4282 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510934.pdf [firstpage_image] =>[orig_patent_app_number] => 168832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3603720 [patent_doc_number] => 05586296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Cache control system and method for selectively performing a non-cache access for instruction data depending on memory line access frequency' [patent_app_type] => 1 [patent_app_number] => 8/156532 [patent_app_country] => US [patent_app_date] => 1993-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3157 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586296.pdf [firstpage_image] =>[orig_patent_app_number] => 156532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3028478 [patent_doc_number] => 05341492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Frame conversion circuit including initial value input circuit' [patent_app_type] => 1 [patent_app_number] => 8/155159 [patent_app_country] => US [patent_app_date] => 1993-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2348 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341492.pdf [firstpage_image] =>[orig_patent_app_number] => 155159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544453 [patent_doc_number] => 05584021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Binary output signal programmer using stored start and end location and timing signal states' [patent_app_type] => 1 [patent_app_number] => 8/141883 [patent_app_country] => US [patent_app_date] => 1993-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3540 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584021.pdf [firstpage_image] =>[orig_patent_app_number] => 141883 [rel_patent_id] =>[rel_patent_doc_number] =>)