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Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3544453 [patent_doc_number] => 05584021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Binary output signal programmer using stored start and end location and timing signal states' [patent_app_type] => 1 [patent_app_number] => 8/141883 [patent_app_country] => US [patent_app_date] => 1993-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3540 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584021.pdf [firstpage_image] =>[orig_patent_app_number] => 141883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141883
Binary output signal programmer using stored start and end location and timing signal states Oct 26, 1993 Issued
08/143293 METHOD AND CIRCUITRY FOR QUEUING AND ABSORBING ERASE COMMANDS IN A MEMORY DEVICE Oct 25, 1993 Abandoned
Array ( [id] => 3079559 [patent_doc_number] => 05353430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Method of operating a cache system including determining an elapsed time or amount of data written to cache prior to writing to main storage' [patent_app_type] => 1 [patent_app_number] => 8/139559 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 16616 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353430.pdf [firstpage_image] =>[orig_patent_app_number] => 139559 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/139559
Method of operating a cache system including determining an elapsed time or amount of data written to cache prior to writing to main storage Oct 19, 1993 Issued
Array ( [id] => 3435499 [patent_doc_number] => 05404327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Memory device with end of cycle precharge utilizing write signal and data transition detectors' [patent_app_type] => 1 [patent_app_number] => 8/131103 [patent_app_country] => US [patent_app_date] => 1993-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5752 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404327.pdf [firstpage_image] =>[orig_patent_app_number] => 131103 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/131103
Memory device with end of cycle precharge utilizing write signal and data transition detectors Oct 3, 1993 Issued
08/127832 COMPUTER SYSTEM INCLUDING A DUAL MEMORY CONFIGURATION WHICH SUPPORTS ON LINE MEMORY EXHACTION AND INSERTION Sep 27, 1993 Abandoned
Array ( [id] => 3848173 [patent_doc_number] => 05740404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Digital signal processor with on-chip select decoder and wait state generator' [patent_app_type] => 1 [patent_app_number] => 8/127682 [patent_app_country] => US [patent_app_date] => 1993-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 11527 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740404.pdf [firstpage_image] =>[orig_patent_app_number] => 127682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/127682
Digital signal processor with on-chip select decoder and wait state generator Sep 26, 1993 Issued
Array ( [id] => 3632371 [patent_doc_number] => 05642496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method of making a backup copy of a memory over a plurality of copying sessions' [patent_app_type] => 1 [patent_app_number] => 8/125943 [patent_app_country] => US [patent_app_date] => 1993-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3186 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642496.pdf [firstpage_image] =>[orig_patent_app_number] => 125943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/125943
Method of making a backup copy of a memory over a plurality of copying sessions Sep 22, 1993 Issued
Array ( [id] => 3603606 [patent_doc_number] => 05586288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Memory interface chip with rapid search capability' [patent_app_type] => 1 [patent_app_number] => 8/125315 [patent_app_country] => US [patent_app_date] => 1993-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 7285 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586288.pdf [firstpage_image] =>[orig_patent_app_number] => 125315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/125315
Memory interface chip with rapid search capability Sep 21, 1993 Issued
Array ( [id] => 3708972 [patent_doc_number] => 05678022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Storage control system with auxiliary storage and optimized process data length and gap to reduce track and cylinder switching' [patent_app_type] => 1 [patent_app_number] => 8/124192 [patent_app_country] => US [patent_app_date] => 1993-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3183 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678022.pdf [firstpage_image] =>[orig_patent_app_number] => 124192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/124192
Storage control system with auxiliary storage and optimized process data length and gap to reduce track and cylinder switching Sep 20, 1993 Issued
08/120699 COMPUTER SYSTEM WITH MULTI-BUFFER DATA CACHE Sep 12, 1993 Abandoned
Array ( [id] => 3126010 [patent_doc_number] => 05414829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Override timing control circuitry and method for terminating program and erase sequences in a flash memory' [patent_app_type] => 1 [patent_app_number] => 8/119892 [patent_app_country] => US [patent_app_date] => 1993-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8200 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414829.pdf [firstpage_image] =>[orig_patent_app_number] => 119892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/119892
Override timing control circuitry and method for terminating program and erase sequences in a flash memory Sep 9, 1993 Issued
Array ( [id] => 3503220 [patent_doc_number] => 05561777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Process for sequentially reading a page from an image memory in either of two directions' [patent_app_type] => 1 [patent_app_number] => 8/114552 [patent_app_country] => US [patent_app_date] => 1993-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2312 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561777.pdf [firstpage_image] =>[orig_patent_app_number] => 114552 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/114552
Process for sequentially reading a page from an image memory in either of two directions Aug 29, 1993 Issued
Array ( [id] => 3440909 [patent_doc_number] => 05463756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics' [patent_app_type] => 1 [patent_app_number] => 8/102119 [patent_app_country] => US [patent_app_date] => 1993-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5406 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463756.pdf [firstpage_image] =>[orig_patent_app_number] => 102119 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/102119
Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics Aug 3, 1993 Issued
08/101095 REQUEST CANCEL SYSTEM Aug 2, 1993 Abandoned
08/100824 MODULAR HIGH-CAPACITY SOLID-STATE MASS DATA STORAGE DEVICE FOR VIDEO SERVERS Aug 1, 1993 Pending
08/099192 METHOD AND SYSTEM FOR PERFORMING CLEAN-UP OF A SOLID STATE DISK DURING HOST COMMAND EXECUTION Jul 28, 1993 Pending
Array ( [id] => 3547379 [patent_doc_number] => 05557744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors' [patent_app_type] => 1 [patent_app_number] => 8/104482 [patent_app_country] => US [patent_app_date] => 1993-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5258 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557744.pdf [firstpage_image] =>[orig_patent_app_number] => 104482 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/104482
Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors Jul 27, 1993 Issued
Array ( [id] => 3122291 [patent_doc_number] => 05408632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Semiconductor memory having a bit position decoder and date re-ordering circuitry for arranging bits in a word of data' [patent_app_type] => 1 [patent_app_number] => 8/096858 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4461 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408632.pdf [firstpage_image] =>[orig_patent_app_number] => 096858 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/096858
Semiconductor memory having a bit position decoder and date re-ordering circuitry for arranging bits in a word of data Jul 25, 1993 Issued
08/092302 APPARATUS AND METHOD FOR ADDRESS PIPELINING OF DYNAMIC RANDOM ACCESS MEMORY Jul 13, 1993 Pending
Array ( [id] => 3035340 [patent_doc_number] => 05327549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Data storage system including a BIOS extension memory on an adapter between a host computer and disk drive' [patent_app_type] => 1 [patent_app_number] => 8/089427 [patent_app_country] => US [patent_app_date] => 1993-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3027 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327549.pdf [firstpage_image] =>[orig_patent_app_number] => 089427 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089427
Data storage system including a BIOS extension memory on an adapter between a host computer and disk drive Jul 7, 1993 Issued
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