Danielle Jackson

Array ( [id] => 3437939 [patent_doc_number] => 05404486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Processor having a stall cache and associated method for preventing instruction stream stalls during load and store instructions in a pipelined computer system' [patent_app_type] => 1 [patent_app_number] => 8/088572 [patent_app_country] => US [patent_app_date] => 1993-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4085 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404486.pdf [firstpage_image] =>[orig_patent_app_number] => 088572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3427067 [patent_doc_number] => 05454094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Method and apparatus for detecting multiple matches in a content addressable memory' [patent_app_type] => 1 [patent_app_number] => 8/081988 [patent_app_country] => US [patent_app_date] => 1993-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2509 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/454/05454094.pdf [firstpage_image] =>[orig_patent_app_number] => 081988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532151 [patent_doc_number] => 05530828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories' [patent_app_type] => 1 [patent_app_number] => 8/079550 [patent_app_country] => US [patent_app_date] => 1993-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530828.pdf [firstpage_image] =>[orig_patent_app_number] => 079550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3064748 [patent_doc_number] => 05325509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations' [patent_app_type] => 1 [patent_app_number] => 8/079966 [patent_app_country] => US [patent_app_date] => 1993-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 14576 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325509.pdf [firstpage_image] =>[orig_patent_app_number] => 079966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3076341 [patent_doc_number] => 05336952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Semiconductor integrated circuit protected from element breakdown by reducing the electric field between the gate and drain or source of a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/067102 [patent_app_country] => US [patent_app_date] => 1993-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 77 [patent_no_of_words] => 16817 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/336/05336952.pdf [firstpage_image] =>[orig_patent_app_number] => 067102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3497619 [patent_doc_number] => 05426763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Memory cartridge including a key detector for inhibiting memory access and preventing undesirable write operations' [patent_app_type] => 1 [patent_app_number] => 8/063774 [patent_app_country] => US [patent_app_date] => 1993-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426763.pdf [firstpage_image] =>[orig_patent_app_number] => 063774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3082169 [patent_doc_number] => 05361343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Microprocessor system including first and second nonvolatile memory arrays which may be simultaneously read and reprogrammed' [patent_app_type] => 1 [patent_app_number] => 8/060828 [patent_app_country] => US [patent_app_date] => 1993-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8735 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361343.pdf [firstpage_image] =>[orig_patent_app_number] => 060828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3625648 [patent_doc_number] => 05566319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'System and method for controlling access to data shared by a plurality of processors using lock files' [patent_app_type] => 1 [patent_app_number] => 8/058702 [patent_app_country] => US [patent_app_date] => 1993-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3609 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566319.pdf [firstpage_image] =>[orig_patent_app_number] => 058702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3564365 [patent_doc_number] => 05572700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Cache access controller and method for permitting caching of information in selected cache lines' [patent_app_type] => 1 [patent_app_number] => 8/055962 [patent_app_country] => US [patent_app_date] => 1993-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2958 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572700.pdf [firstpage_image] =>[orig_patent_app_number] => 055962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3602767 [patent_doc_number] => 05488711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Serial EEPROM device and associated method for reducing data load time using a page mode write cache' [patent_app_type] => 1 [patent_app_number] => 8/041076 [patent_app_country] => US [patent_app_date] => 1993-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3675 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488711.pdf [firstpage_image] =>[orig_patent_app_number] => 041076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3058830 [patent_doc_number] => 05287485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Digital processing system including plural memory devices and data transfer circuitry' [patent_app_type] => 1 [patent_app_number] => 8/041129 [patent_app_country] => US [patent_app_date] => 1993-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8678 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287485.pdf [firstpage_image] =>[orig_patent_app_number] => 041129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061748 [patent_doc_number] => 05307309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Memory module having on-chip surge capacitors' [patent_app_type] => 1 [patent_app_number] => 8/034001 [patent_app_country] => US [patent_app_date] => 1993-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2820 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307309.pdf [firstpage_image] =>[orig_patent_app_number] => 034001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612239 [patent_doc_number] => 05559980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method and apparatus for detecting references to deallocated memory in a dynamic memory allocation system' [patent_app_type] => 1 [patent_app_number] => 8/032918 [patent_app_country] => US [patent_app_date] => 1993-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4582 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559980.pdf [firstpage_image] =>[orig_patent_app_number] => 032918 [rel_patent_id] =>[rel_patent_doc_number] =>)