| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3499709
[patent_doc_number] => 05440509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines'
[patent_app_type] => 1
[patent_app_number] => 8/022392
[patent_app_country] => US
[patent_app_date] => 1993-02-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/440/05440509.pdf
[firstpage_image] =>[orig_patent_app_number] => 022392
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/022392 | Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines | Feb 23, 1993 | Issued |
Array
(
[id] => 3601189
[patent_doc_number] => 05568415
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Content addressable memory having a pair of memory cells storing don\'t care states for address translation'
[patent_app_type] => 1
[patent_app_number] => 8/021510
[patent_app_country] => US
[patent_app_date] => 1993-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 8758
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568415.pdf
[firstpage_image] =>[orig_patent_app_number] => 021510
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/021510 | Content addressable memory having a pair of memory cells storing don't care states for address translation | Feb 18, 1993 | Issued |
Array
(
[id] => 3107156
[patent_doc_number] => 05313612
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Information recording and reproducing apparatus including both data and work optical disk drives for restoring data and commands after a malfunction'
[patent_app_type] => 1
[patent_app_number] => 8/022418
[patent_app_country] => US
[patent_app_date] => 1993-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3916
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/313/05313612.pdf
[firstpage_image] =>[orig_patent_app_number] => 022418
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/022418 | Information recording and reproducing apparatus including both data and work optical disk drives for restoring data and commands after a malfunction | Feb 15, 1993 | Issued |
| 08/011412 | MEMORY ACCESSING DEVICE WITH ENHANCED PIPELINE PROCESSING/BUS USE MANAGEMENT | Jan 28, 1993 | Abandoned |
Array
(
[id] => 3059788
[patent_doc_number] => 05287536
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Nonvolatile memory array wordline driver circuit with voltage translator circuit'
[patent_app_type] => 1
[patent_app_number] => 8/009276
[patent_app_country] => US
[patent_app_date] => 1993-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 5049
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/287/05287536.pdf
[firstpage_image] =>[orig_patent_app_number] => 009276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/009276 | Nonvolatile memory array wordline driver circuit with voltage translator circuit | Jan 21, 1993 | Issued |
Array
(
[id] => 3099724
[patent_doc_number] => 05278802
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Decoding global drive/boot signals using local predecoders'
[patent_app_type] => 1
[patent_app_number] => 8/000913
[patent_app_country] => US
[patent_app_date] => 1993-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4780
[patent_no_of_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/278/05278802.pdf
[firstpage_image] =>[orig_patent_app_number] => 000913
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/000913 | Decoding global drive/boot signals using local predecoders | Jan 5, 1993 | Issued |
Array
(
[id] => 3102780
[patent_doc_number] => 05278964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache'
[patent_app_type] => 1
[patent_app_number] => 8/000793
[patent_app_country] => US
[patent_app_date] => 1993-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/278/05278964.pdf
[firstpage_image] =>[orig_patent_app_number] => 000793
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/000793 | Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache | Jan 3, 1993 | Issued |
| 07/999046 | METHOD AND APPARATUS FOR EMPLOYING TWO BUSES FOR SYSTEM AND DIRECT VRAM INTERFACE | Dec 30, 1992 | Abandoned |
| 07/999490 | PERIPHERAL COMPONENT INTERFACE | Dec 30, 1992 | Abandoned |
Array
(
[id] => 3564546
[patent_doc_number] => 05493665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Portable memory device and method of securing the integrity of stored data therein utilizing a starting address and a stored memory cycle number'
[patent_app_type] => 1
[patent_app_number] => 7/994382
[patent_app_country] => US
[patent_app_date] => 1992-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3110
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/493/05493665.pdf
[firstpage_image] =>[orig_patent_app_number] => 994382
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/994382 | Portable memory device and method of securing the integrity of stored data therein utilizing a starting address and a stored memory cycle number | Dec 20, 1992 | Issued |
| 07/991812 | STORAGE CONTROLLER WITH IMPROVED NONVOLATILE MEMORY FAILURE RECOVERY SYSTEM | Dec 16, 1992 | Abandoned |
Array
(
[id] => 3120472
[patent_doc_number] => 05418926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'System and method for indicating whether a block size in a detachable memory device corresponds to a predetermined broadcasting system standard'
[patent_app_type] => 1
[patent_app_number] => 7/987240
[patent_app_country] => US
[patent_app_date] => 1992-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/05/418/05418926.pdf
[firstpage_image] =>[orig_patent_app_number] => 987240
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/987240 | System and method for indicating whether a block size in a detachable memory device corresponds to a predetermined broadcasting system standard | Dec 6, 1992 | Issued |
Array
(
[id] => 3063340
[patent_doc_number] => 05305445
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-19
[patent_title] => 'System and method employing extended memory capacity detection'
[patent_app_type] => 1
[patent_app_number] => 7/985225
[patent_app_country] => US
[patent_app_date] => 1992-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/305/05305445.pdf
[firstpage_image] =>[orig_patent_app_number] => 985225
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/985225 | System and method employing extended memory capacity detection | Nov 30, 1992 | Issued |
Array
(
[id] => 3601228
[patent_doc_number] => 05551010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU'
[patent_app_type] => 1
[patent_app_number] => 7/978882
[patent_app_country] => US
[patent_app_date] => 1992-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
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[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/551/05551010.pdf
[firstpage_image] =>[orig_patent_app_number] => 978882
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/978882 | Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU | Nov 18, 1992 | Issued |
| 07/977232 | DYNAMIC CACHE COHERENCY METHOD AND APPARATUS | Nov 15, 1992 | Abandoned |
Array
(
[id] => 3110874
[patent_doc_number] => 05293623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Random access memory based buffer memory and associated method utilizing pipelined look-ahead reading'
[patent_app_type] => 1
[patent_app_number] => 7/976719
[patent_app_country] => US
[patent_app_date] => 1992-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/05/293/05293623.pdf
[firstpage_image] =>[orig_patent_app_number] => 976719
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/976719 | Random access memory based buffer memory and associated method utilizing pipelined look-ahead reading | Nov 15, 1992 | Issued |
| 07/971565 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH AN IMPROVED COUPLING ARRANGEMENT FOR LOGIC UNITS ON LOGIC BLOCKS | Nov 4, 1992 | Abandoned |
Array
(
[id] => 3109704
[patent_doc_number] => 05293560
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Multi-state flash EEPROM system using incremental programing and erasing methods'
[patent_app_type] => 1
[patent_app_number] => 7/970949
[patent_app_country] => US
[patent_app_date] => 1992-11-03
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[pdf_file] => patents/05/293/05293560.pdf
[firstpage_image] =>[orig_patent_app_number] => 970949
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/970949 | Multi-state flash EEPROM system using incremental programing and erasing methods | Nov 2, 1992 | Issued |
Array
(
[id] => 3704766
[patent_doc_number] => 05596543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Semiconductor memory device including circuitry for activating and deactivating a word line within a single RAS cycle'
[patent_app_type] => 1
[patent_app_number] => 7/969363
[patent_app_country] => US
[patent_app_date] => 1992-10-30
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[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/05/596/05596543.pdf
[firstpage_image] =>[orig_patent_app_number] => 969363
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/969363 | Semiconductor memory device including circuitry for activating and deactivating a word line within a single RAS cycle | Oct 29, 1992 | Issued |
Array
(
[id] => 3547698
[patent_doc_number] => 05557766
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-17
[patent_title] => 'High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank'
[patent_app_type] => 1
[patent_app_number] => 7/964142
[patent_app_country] => US
[patent_app_date] => 1992-10-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/557/05557766.pdf
[firstpage_image] =>[orig_patent_app_number] => 964142
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/964142 | High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank | Oct 20, 1992 | Issued |