Danielle Jackson

Array ( [id] => 3454690 [patent_doc_number] => 05467461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Multiprocessor computer system having bus control circuitry for transferring data between microcomputers' [patent_app_type] => 1 [patent_app_number] => 7/910780 [patent_app_country] => US [patent_app_date] => 1992-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9524 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467461.pdf [firstpage_image] =>[orig_patent_app_number] => 910780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3024374 [patent_doc_number] => 05276849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Apparatus and method for maintaining cache/main memory consistency utilizing a dual port FIFO buffer' [patent_app_type] => 1 [patent_app_number] => 7/912055 [patent_app_country] => US [patent_app_date] => 1992-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3700 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276849.pdf [firstpage_image] =>[orig_patent_app_number] => 912055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2979506 [patent_doc_number] => 05258954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Semiconductor memory including circuitry for driving plural word lines in a test mode' [patent_app_type] => 1 [patent_app_number] => 7/908744 [patent_app_country] => US [patent_app_date] => 1992-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3770 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258954.pdf [firstpage_image] =>[orig_patent_app_number] => 908744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3626170 [patent_doc_number] => 05535350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Cache memory unit including a replacement address register and address update circuitry for reduced cache overhead' [patent_app_type] => 1 [patent_app_number] => 7/907920 [patent_app_country] => US [patent_app_date] => 1992-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3610 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535350.pdf [firstpage_image] =>[orig_patent_app_number] => 907920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600199 [patent_doc_number] => 05553267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method and apparatus for coordinating access to and modifying multiple element data objects in a shared memory' [patent_app_type] => 1 [patent_app_number] => 7/907330 [patent_app_country] => US [patent_app_date] => 1992-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6535 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553267.pdf [firstpage_image] =>[orig_patent_app_number] => 907330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3016562 [patent_doc_number] => 05375220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Multiprocessor system including a cache memory with tag copy units' [patent_app_type] => 1 [patent_app_number] => 7/906502 [patent_app_country] => US [patent_app_date] => 1992-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6900 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 471 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375220.pdf [firstpage_image] =>[orig_patent_app_number] => 906502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3497513 [patent_doc_number] => 05426755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Semiconductor device including clock selection circuitry selecting between high and low frequency clock signals for reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 7/904532 [patent_app_country] => US [patent_app_date] => 1992-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4440 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426755.pdf [firstpage_image] =>[orig_patent_app_number] => 904532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601378 [patent_doc_number] => 05517634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Disk drive system including a DRAM array and associated method for programming initial information into the array' [patent_app_type] => 1 [patent_app_number] => 7/903001 [patent_app_country] => US [patent_app_date] => 1992-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4918 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517634.pdf [firstpage_image] =>[orig_patent_app_number] => 903001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488377 [patent_doc_number] => 05432918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Method and apparatus for ordering read and write operations using conflict bits in a write queue' [patent_app_type] => 1 [patent_app_number] => 7/901646 [patent_app_country] => US [patent_app_date] => 1992-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 25756 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432918.pdf [firstpage_image] =>[orig_patent_app_number] => 901646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3437881 [patent_doc_number] => 05404482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills' [patent_app_type] => 1 [patent_app_number] => 7/902122 [patent_app_country] => US [patent_app_date] => 1992-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 26813 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404482.pdf [firstpage_image] =>[orig_patent_app_number] => 902122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3083136 [patent_doc_number] => 05361391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Intelligent cache memory and prefetch method based on CPU data fetching characteristics' [patent_app_type] => 1 [patent_app_number] => 7/901803 [patent_app_country] => US [patent_app_date] => 1992-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4107 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 728 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361391.pdf [firstpage_image] =>[orig_patent_app_number] => 901803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3437895 [patent_doc_number] => 05404483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills' [patent_app_type] => 1 [patent_app_number] => 7/902156 [patent_app_country] => US [patent_app_date] => 1992-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 26574 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404483.pdf [firstpage_image] =>[orig_patent_app_number] => 902156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3501544 [patent_doc_number] => 05471601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Memory device and method for avoiding live lock of a DRAM with cache' [patent_app_type] => 1 [patent_app_number] => 7/900180 [patent_app_country] => US [patent_app_date] => 1992-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3382 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471601.pdf [firstpage_image] =>[orig_patent_app_number] => 900180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3671266 [patent_doc_number] => 05659797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface' [patent_app_type] => 1 [patent_app_number] => 7/896062 [patent_app_country] => US [patent_app_date] => 1992-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6118 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659797.pdf [firstpage_image] =>[orig_patent_app_number] => 896062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3012348 [patent_doc_number] => 05359726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Ferroelectric storage device used in place of a rotating disk drive unit in a computer system' [patent_app_type] => 1 [patent_app_number] => 7/895328 [patent_app_country] => US [patent_app_date] => 1992-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3617 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359726.pdf [firstpage_image] =>[orig_patent_app_number] => 895328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3019284 [patent_doc_number] => 05331596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Address multiplexed dynamic RAM having a test mode capability' [patent_app_type] => 1 [patent_app_number] => 7/887802 [patent_app_country] => US [patent_app_date] => 1992-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5544 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/331/05331596.pdf [firstpage_image] =>[orig_patent_app_number] => 887802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3075522 [patent_doc_number] => 05295117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Semiconductor memory device and method for controlling an output buffer utilizing an address transition detector' [patent_app_type] => 1 [patent_app_number] => 7/884276 [patent_app_country] => US [patent_app_date] => 1992-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4222 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295117.pdf [firstpage_image] =>[orig_patent_app_number] => 884276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3082093 [patent_doc_number] => 05361339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines' [patent_app_type] => 1 [patent_app_number] => 7/878192 [patent_app_country] => US [patent_app_date] => 1992-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2500 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361339.pdf [firstpage_image] =>[orig_patent_app_number] => 878192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2896355 [patent_doc_number] => 05214601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers' [patent_app_type] => 1 [patent_app_number] => 7/876690 [patent_app_country] => US [patent_app_date] => 1992-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8623 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214601.pdf [firstpage_image] =>[orig_patent_app_number] => 876690 [rel_patent_id] =>[rel_patent_doc_number] =>)