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Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3473359 [patent_doc_number] => 05392412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Data communication controller for use with a single-port data packet buffer' [patent_app_type] => 1 [patent_app_number] => 7/770695 [patent_app_country] => US [patent_app_date] => 1991-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10196 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 758 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392412.pdf [firstpage_image] =>[orig_patent_app_number] => 770695 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/770695
Data communication controller for use with a single-port data packet buffer Oct 2, 1991 Issued
07/764769 DYNAMIC RANDOM ACCESS MEMORY HAVING BIPOLAR AND C-MOS TRANSISTOR Sep 23, 1991 Abandoned
07/763368 DIGITAL DATA PROCESSOR WITH IMPROVED PAGING Sep 19, 1991 Abandoned
07/763132 DIGITAL DATA PROCESSOR WITH DISTRIBUTED MEMORY SYSTEM Sep 19, 1991 Abandoned
Array ( [id] => 3454305 [patent_doc_number] => 05430860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence' [patent_app_type] => 1 [patent_app_number] => 7/761095 [patent_app_country] => US [patent_app_date] => 1991-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4397 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430860.pdf [firstpage_image] =>[orig_patent_app_number] => 761095 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/761095
Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence Sep 16, 1991 Issued
Array ( [id] => 2969846 [patent_doc_number] => 05198999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Serial input/output semiconductor memory including an output data latch circuit' [patent_app_type] => 1 [patent_app_number] => 7/754170 [patent_app_country] => US [patent_app_date] => 1991-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5998 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198999.pdf [firstpage_image] =>[orig_patent_app_number] => 754170 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/754170
Serial input/output semiconductor memory including an output data latch circuit Sep 3, 1991 Issued
07/754816 METHOD AND APPARATUS FOR RAPID DATA COPYING USING REASSIGNED BACKING PAGES Sep 3, 1991 Abandoned
07/747202 HIGH-PERFORMANCE DYNAMIC MEMORY SYSTEM Aug 15, 1991 Abandoned
Array ( [id] => 2796999 [patent_doc_number] => 05155705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Semiconductor memory device having flash write function' [patent_app_type] => 1 [patent_app_number] => 7/746011 [patent_app_country] => US [patent_app_date] => 1991-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5432 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155705.pdf [firstpage_image] =>[orig_patent_app_number] => 746011 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/746011
Semiconductor memory device having flash write function Aug 12, 1991 Issued
Array ( [id] => 3454289 [patent_doc_number] => 05430859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Solid state memory system including plural memory chips and a serialized bus' [patent_app_type] => 1 [patent_app_number] => 7/736733 [patent_app_country] => US [patent_app_date] => 1991-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9293 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430859.pdf [firstpage_image] =>[orig_patent_app_number] => 736733 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/736733
Solid state memory system including plural memory chips and a serialized bus Jul 25, 1991 Issued
07/733972 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH NAND CELL STRUCTURE Jul 21, 1991 Abandoned
07/722220 ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY WITH NAND CELL STRUCTURE Jun 26, 1991 Abandoned
Array ( [id] => 2843092 [patent_doc_number] => 05175840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Microcomputer having a PROM including data security and test circuitry' [patent_app_type] => 1 [patent_app_number] => 7/726113 [patent_app_country] => US [patent_app_date] => 1991-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4854 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175840.pdf [firstpage_image] =>[orig_patent_app_number] => 726113 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/726113
Microcomputer having a PROM including data security and test circuitry Jun 20, 1991 Issued
07/714321 MEMORY DEVICE HAVING A NON-UNIFORM REDUNDANCY DECODER ARRANGEMENT Jun 10, 1991 Abandoned
Array ( [id] => 2925350 [patent_doc_number] => 05237674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Self identifying scheme for memory module including circuitry for identfying accessing speed' [patent_app_type] => 1 [patent_app_number] => 7/713639 [patent_app_country] => US [patent_app_date] => 1991-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2616 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237674.pdf [firstpage_image] =>[orig_patent_app_number] => 713639 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/713639
Self identifying scheme for memory module including circuitry for identfying accessing speed Jun 9, 1991 Issued
Array ( [id] => 3110638 [patent_doc_number] => 05293610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Memory system having two-level security system for enhanced protection against unauthorized access' [patent_app_type] => 1 [patent_app_number] => 7/713046 [patent_app_country] => US [patent_app_date] => 1991-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2854 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293610.pdf [firstpage_image] =>[orig_patent_app_number] => 713046 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/713046
Memory system having two-level security system for enhanced protection against unauthorized access Jun 9, 1991 Issued
Array ( [id] => 2847724 [patent_doc_number] => 05161121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Random access memory including word line clamping circuits' [patent_app_type] => 1 [patent_app_number] => 7/711325 [patent_app_country] => US [patent_app_date] => 1991-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3034 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161121.pdf [firstpage_image] =>[orig_patent_app_number] => 711325 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/711325
Random access memory including word line clamping circuits Jun 5, 1991 Issued
Array ( [id] => 3004186 [patent_doc_number] => 05367485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Semiconductor memory device including output latches for improved merging of output data' [patent_app_type] => 1 [patent_app_number] => 7/711571 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3764 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367485.pdf [firstpage_image] =>[orig_patent_app_number] => 711571 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/711571
Semiconductor memory device including output latches for improved merging of output data Jun 2, 1991 Issued
Array ( [id] => 2815611 [patent_doc_number] => 05148399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 7/709808 [patent_app_country] => US [patent_app_date] => 1991-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 4200 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148399.pdf [firstpage_image] =>[orig_patent_app_number] => 709808 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/709808
Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory May 30, 1991 Issued
Array ( [id] => 3435466 [patent_doc_number] => 05423015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Memory structure and method for shuffling a stack of data utilizing buffer memory locations' [patent_app_type] => 1 [patent_app_number] => 7/700132 [patent_app_country] => US [patent_app_date] => 1991-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 11611 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/423/05423015.pdf [firstpage_image] =>[orig_patent_app_number] => 700132 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/700132
Memory structure and method for shuffling a stack of data utilizing buffer memory locations May 20, 1991 Issued
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