| Application number | Title of the application | Filing Date | Status |
|---|
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[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Data communication controller for use with a single-port data packet buffer'
[patent_app_type] => 1
[patent_app_number] => 7/770695
[patent_app_country] => US
[patent_app_date] => 1991-10-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/770695 | Data communication controller for use with a single-port data packet buffer | Oct 2, 1991 | Issued |
| 07/764769 | DYNAMIC RANDOM ACCESS MEMORY HAVING BIPOLAR AND C-MOS TRANSISTOR | Sep 23, 1991 | Abandoned |
| 07/763368 | DIGITAL DATA PROCESSOR WITH IMPROVED PAGING | Sep 19, 1991 | Abandoned |
| 07/763132 | DIGITAL DATA PROCESSOR WITH DISTRIBUTED MEMORY SYSTEM | Sep 19, 1991 | Abandoned |
Array
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[patent_doc_number] => 05430860
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence'
[patent_app_type] => 1
[patent_app_number] => 7/761095
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[patent_app_date] => 1991-09-17
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[firstpage_image] =>[orig_patent_app_number] => 761095
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/761095 | Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence | Sep 16, 1991 | Issued |
Array
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[id] => 2969846
[patent_doc_number] => 05198999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Serial input/output semiconductor memory including an output data latch circuit'
[patent_app_type] => 1
[patent_app_number] => 7/754170
[patent_app_country] => US
[patent_app_date] => 1991-09-04
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[firstpage_image] =>[orig_patent_app_number] => 754170
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/754170 | Serial input/output semiconductor memory including an output data latch circuit | Sep 3, 1991 | Issued |
| 07/754816 | METHOD AND APPARATUS FOR RAPID DATA COPYING USING REASSIGNED BACKING PAGES | Sep 3, 1991 | Abandoned |
| 07/747202 | HIGH-PERFORMANCE DYNAMIC MEMORY SYSTEM | Aug 15, 1991 | Abandoned |
Array
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[id] => 2796999
[patent_doc_number] => 05155705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Semiconductor memory device having flash write function'
[patent_app_type] => 1
[patent_app_number] => 7/746011
[patent_app_country] => US
[patent_app_date] => 1991-08-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/746011 | Semiconductor memory device having flash write function | Aug 12, 1991 | Issued |
Array
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[id] => 3454289
[patent_doc_number] => 05430859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Solid state memory system including plural memory chips and a serialized bus'
[patent_app_type] => 1
[patent_app_number] => 7/736733
[patent_app_country] => US
[patent_app_date] => 1991-07-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/736733 | Solid state memory system including plural memory chips and a serialized bus | Jul 25, 1991 | Issued |
| 07/733972 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH NAND CELL STRUCTURE | Jul 21, 1991 | Abandoned |
| 07/722220 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY WITH NAND CELL STRUCTURE | Jun 26, 1991 | Abandoned |
Array
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[id] => 2843092
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[patent_issue_date] => 1992-12-29
[patent_title] => 'Microcomputer having a PROM including data security and test circuitry'
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[firstpage_image] =>[orig_patent_app_number] => 726113
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/726113 | Microcomputer having a PROM including data security and test circuitry | Jun 20, 1991 | Issued |
| 07/714321 | MEMORY DEVICE HAVING A NON-UNIFORM REDUNDANCY DECODER ARRANGEMENT | Jun 10, 1991 | Abandoned |
Array
(
[id] => 2925350
[patent_doc_number] => 05237674
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[patent_kind] => NA
[patent_issue_date] => 1993-08-17
[patent_title] => 'Self identifying scheme for memory module including circuitry for identfying accessing speed'
[patent_app_type] => 1
[patent_app_number] => 7/713639
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[firstpage_image] =>[orig_patent_app_number] => 713639
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/713639 | Self identifying scheme for memory module including circuitry for identfying accessing speed | Jun 9, 1991 | Issued |
Array
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[id] => 3110638
[patent_doc_number] => 05293610
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Memory system having two-level security system for enhanced protection against unauthorized access'
[patent_app_type] => 1
[patent_app_number] => 7/713046
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/713046 | Memory system having two-level security system for enhanced protection against unauthorized access | Jun 9, 1991 | Issued |
Array
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[patent_issue_date] => 1992-11-03
[patent_title] => 'Random access memory including word line clamping circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/711325 | Random access memory including word line clamping circuits | Jun 5, 1991 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/711571 | Semiconductor memory device including output latches for improved merging of output data | Jun 2, 1991 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/700132 | Memory structure and method for shuffling a stack of data utilizing buffer memory locations | May 20, 1991 | Issued |