Danielle Jackson

Array ( [id] => 2757954 [patent_doc_number] => 05038326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-06 [patent_title] => 'Static RAM having a precharge operation which exhibits reduced hot electron stress' [patent_app_type] => 1 [patent_app_number] => 7/617306 [patent_app_country] => US [patent_app_date] => 1990-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3770 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/038/05038326.pdf [firstpage_image] =>[orig_patent_app_number] => 617306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2797912 [patent_doc_number] => 05101378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Optimized electrically erasable cell for minimum read disturb and associated method of sensing' [patent_app_type] => 1 [patent_app_number] => 7/604824 [patent_app_country] => US [patent_app_date] => 1990-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6964 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101378.pdf [firstpage_image] =>[orig_patent_app_number] => 604824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2758650 [patent_doc_number] => 05031151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty' [patent_app_type] => 1 [patent_app_number] => 7/600944 [patent_app_country] => US [patent_app_date] => 1990-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4459 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031151.pdf [firstpage_image] =>[orig_patent_app_number] => 600944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2773335 [patent_doc_number] => 05063539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-05 [patent_title] => 'Ferroelectric memory with diode isolation' [patent_app_type] => 1 [patent_app_number] => 7/593528 [patent_app_country] => US [patent_app_date] => 1990-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3180 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/063/05063539.pdf [firstpage_image] =>[orig_patent_app_number] => 593528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3064550 [patent_doc_number] => 05325499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory' [patent_app_type] => 1 [patent_app_number] => 7/590671 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14346 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325499.pdf [firstpage_image] =>[orig_patent_app_number] => 590671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2770212 [patent_doc_number] => 05060198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-22 [patent_title] => 'Device for the structural testing of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/587512 [patent_app_country] => US [patent_app_date] => 1990-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2985 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/060/05060198.pdf [firstpage_image] =>[orig_patent_app_number] => 587512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3111125 [patent_doc_number] => 05319762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Associative memory capable of matching a variable indicator in one string of characters with a portion of another string' [patent_app_type] => 1 [patent_app_number] => 7/578932 [patent_app_country] => US [patent_app_date] => 1990-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 11996 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319762.pdf [firstpage_image] =>[orig_patent_app_number] => 578932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2785726 [patent_doc_number] => 05132930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines' [patent_app_type] => 1 [patent_app_number] => 7/577062 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3950 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 815 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132930.pdf [firstpage_image] =>[orig_patent_app_number] => 577062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3127655 [patent_doc_number] => 05396605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Buffer storage control apparatus including a translation lookaside buffer and an improved address comparator layout arrangement' [patent_app_type] => 1 [patent_app_number] => 7/565133 [patent_app_country] => US [patent_app_date] => 1990-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5482 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396605.pdf [firstpage_image] =>[orig_patent_app_number] => 565133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2894380 [patent_doc_number] => 05268870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Flash EEPROM system and intelligent programming and erasing methods therefor' [patent_app_type] => 1 [patent_app_number] => 7/563287 [patent_app_country] => US [patent_app_date] => 1990-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5886 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268870.pdf [firstpage_image] =>[orig_patent_app_number] => 563287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2963459 [patent_doc_number] => 05263146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Multiprocessor system including an exclusive access controller with lock request holding and grant circuits' [patent_app_type] => 1 [patent_app_number] => 7/558331 [patent_app_country] => US [patent_app_date] => 1990-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1997 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263146.pdf [firstpage_image] =>[orig_patent_app_number] => 558331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2948153 [patent_doc_number] => 05247640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Dual access control system including plural magnetic disk control units and contention control circuitry' [patent_app_type] => 1 [patent_app_number] => 7/558902 [patent_app_country] => US [patent_app_date] => 1990-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 7983 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247640.pdf [firstpage_image] =>[orig_patent_app_number] => 558902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3012275 [patent_doc_number] => 05359722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM' [patent_app_type] => 1 [patent_app_number] => 7/555960 [patent_app_country] => US [patent_app_date] => 1990-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12177 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359722.pdf [firstpage_image] =>[orig_patent_app_number] => 555960 [rel_patent_id] =>[rel_patent_doc_number] =>)