Danielle Jackson

Array ( [id] => 2797930 [patent_doc_number] => 05101379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Apparatus for page mode programming of an EEPROM cell array with false loading protection' [patent_app_type] => 1 [patent_app_number] => 7/551642 [patent_app_country] => US [patent_app_date] => 1990-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6359 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101379.pdf [firstpage_image] =>[orig_patent_app_number] => 551642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2743962 [patent_doc_number] => 05051958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Nonvolatile static memory device utilizing separate power supplies' [patent_app_type] => 1 [patent_app_number] => 7/547525 [patent_app_country] => US [patent_app_date] => 1990-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3471 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 418 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051958.pdf [firstpage_image] =>[orig_patent_app_number] => 547525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2718571 [patent_doc_number] => 05056062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Method of operating an EPROM including delaying and boosting steps' [patent_app_type] => 1 [patent_app_number] => 7/545583 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7712 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/056/05056062.pdf [firstpage_image] =>[orig_patent_app_number] => 545583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3107389 [patent_doc_number] => 05299156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Dual port static RAM with bidirectional shift capability' [patent_app_type] => 1 [patent_app_number] => 7/542689 [patent_app_country] => US [patent_app_date] => 1990-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3263 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/299/05299156.pdf [firstpage_image] =>[orig_patent_app_number] => 542689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2840512 [patent_doc_number] => 05175705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Semiconductor memory device having circuit for prevention of overcharge of column line' [patent_app_type] => 1 [patent_app_number] => 7/542084 [patent_app_country] => US [patent_app_date] => 1990-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3898 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175705.pdf [firstpage_image] =>[orig_patent_app_number] => 542084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2907813 [patent_doc_number] => 05241643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Memory system and associated method for disabling address buffers connected to unused SIMM slots' [patent_app_type] => 1 [patent_app_number] => 7/540651 [patent_app_country] => US [patent_app_date] => 1990-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4827 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241643.pdf [firstpage_image] =>[orig_patent_app_number] => 540651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2976725 [patent_doc_number] => 05274778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'EPROM register providing a full time static output signal' [patent_app_type] => 1 [patent_app_number] => 7/532065 [patent_app_country] => US [patent_app_date] => 1990-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6285 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274778.pdf [firstpage_image] =>[orig_patent_app_number] => 532065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2832069 [patent_doc_number] => 05095462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'FIFO information storage apparatus including status and logic modules for each cell' [patent_app_type] => 1 [patent_app_number] => 7/528864 [patent_app_country] => US [patent_app_date] => 1990-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4545 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095462.pdf [firstpage_image] =>[orig_patent_app_number] => 528864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2655638 [patent_doc_number] => 04980863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Semiconductor memory device having switching circuit for coupling together two pairs of bit lines' [patent_app_type] => 1 [patent_app_number] => 7/517384 [patent_app_country] => US [patent_app_date] => 1990-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3446 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980863.pdf [firstpage_image] =>[orig_patent_app_number] => 517384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3009040 [patent_doc_number] => 05359553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Low power ECL/MOS level converting circuit and memory device and method of converting a signal level' [patent_app_type] => 1 [patent_app_number] => 7/515304 [patent_app_country] => US [patent_app_date] => 1990-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4911 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359553.pdf [firstpage_image] =>[orig_patent_app_number] => 515304 [rel_patent_id] =>[rel_patent_doc_number] =>)