Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
07/501064 NON UNIFORM REDUNDANCY DECODER AND METHOD FOR A MEMORY DEVICE Mar 28, 1990 Abandoned
07/495984 MEMORY APPARATUS COMPRISING MEMORY CARDS Mar 19, 1990 Abandoned
Array ( [id] => 2847379 [patent_doc_number] => 05121354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Random access memory with access on bit boundaries' [patent_app_type] => 1 [patent_app_number] => 7/491894 [patent_app_country] => US [patent_app_date] => 1990-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3827 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121354.pdf [firstpage_image] =>[orig_patent_app_number] => 491894 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/491894
Random access memory with access on bit boundaries Mar 11, 1990 Issued
Array ( [id] => 2757019 [patent_doc_number] => 05016215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing' [patent_app_type] => 1 [patent_app_number] => 7/494784 [patent_app_country] => US [patent_app_date] => 1990-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3396 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/016/05016215.pdf [firstpage_image] =>[orig_patent_app_number] => 494784 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/494784
High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing Mar 11, 1990 Issued
Array ( [id] => 2758526 [patent_doc_number] => 05031144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Ferroelectric memory with non-destructive readout including grid electrode between top and bottom electrodes' [patent_app_type] => 1 [patent_app_number] => 7/486334 [patent_app_country] => US [patent_app_date] => 1990-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2539 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031144.pdf [firstpage_image] =>[orig_patent_app_number] => 486334 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/486334
Ferroelectric memory with non-destructive readout including grid electrode between top and bottom electrodes Feb 27, 1990 Issued
Array ( [id] => 2734899 [patent_doc_number] => 05058066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Output buffer precharge circuit for DRAM' [patent_app_type] => 1 [patent_app_number] => 7/485914 [patent_app_country] => US [patent_app_date] => 1990-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3563 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/058/05058066.pdf [firstpage_image] =>[orig_patent_app_number] => 485914 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/485914
Output buffer precharge circuit for DRAM Feb 26, 1990 Issued
Array ( [id] => 2734880 [patent_doc_number] => 05058065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Memory based line-delay architecture' [patent_app_type] => 1 [patent_app_number] => 7/488824 [patent_app_country] => US [patent_app_date] => 1990-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4580 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/058/05058065.pdf [firstpage_image] =>[orig_patent_app_number] => 488824 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/488824
Memory based line-delay architecture Feb 25, 1990 Issued
07/483965 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MULTIDIRECTION DATA ACCESS Feb 14, 1990 Abandoned
07/473303 SCANNING TUNNELING MICROSCOPE MEMORY APPARATUS INCLUDING TUNNEL CURRENT PROBES Jan 31, 1990 Abandoned
Array ( [id] => 2806761 [patent_doc_number] => 05144581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Apparatus including atomic probes utilizing tunnel current to read, write and erase data' [patent_app_type] => 1 [patent_app_number] => 7/471854 [patent_app_country] => US [patent_app_date] => 1990-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 8501 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/144/05144581.pdf [firstpage_image] =>[orig_patent_app_number] => 471854 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/471854
Apparatus including atomic probes utilizing tunnel current to read, write and erase data Jan 28, 1990 Issued
Array ( [id] => 2810357 [patent_doc_number] => 05140553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Flash writing circuit for writing test data in dynamic random access memory (DRAM) devices' [patent_app_type] => 1 [patent_app_number] => 7/470834 [patent_app_country] => US [patent_app_date] => 1990-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2671 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140553.pdf [firstpage_image] =>[orig_patent_app_number] => 470834 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/470834
Flash writing circuit for writing test data in dynamic random access memory (DRAM) devices Jan 25, 1990 Issued
Array ( [id] => 2716939 [patent_doc_number] => 04982366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Static semiconductor memory with readout inhibit means' [patent_app_type] => 1 [patent_app_number] => 7/467348 [patent_app_country] => US [patent_app_date] => 1990-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2841 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/982/04982366.pdf [firstpage_image] =>[orig_patent_app_number] => 467348 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/467348
Static semiconductor memory with readout inhibit means Jan 21, 1990 Issued
Array ( [id] => 3127734 [patent_doc_number] => 05396609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Method of protecting programs and data in a computer against unauthorized access and modification by monitoring address regions' [patent_app_type] => 1 [patent_app_number] => 7/466960 [patent_app_country] => US [patent_app_date] => 1990-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3036 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 480 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396609.pdf [firstpage_image] =>[orig_patent_app_number] => 466960 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/466960
Method of protecting programs and data in a computer against unauthorized access and modification by monitoring address regions Jan 17, 1990 Issued
Array ( [id] => 2743878 [patent_doc_number] => 05051953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'EEPROM device including read, write, and erase voltage switching circuits' [patent_app_type] => 1 [patent_app_number] => 7/453073 [patent_app_country] => US [patent_app_date] => 1989-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5217 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051953.pdf [firstpage_image] =>[orig_patent_app_number] => 453073 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/453073
EEPROM device including read, write, and erase voltage switching circuits Dec 17, 1989 Issued
Array ( [id] => 2872760 [patent_doc_number] => 05167029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Data processing system and associated process using memory cards having data modify functions utilizing a data mask and an internal register' [patent_app_type] => 1 [patent_app_number] => 7/450182 [patent_app_country] => US [patent_app_date] => 1989-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3658 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/167/05167029.pdf [firstpage_image] =>[orig_patent_app_number] => 450182 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/450182
Data processing system and associated process using memory cards having data modify functions utilizing a data mask and an internal register Dec 12, 1989 Issued
07/446442 MEMORY APPARATUS AND HANDLING APPARATUS THEREFOR Dec 4, 1989 Abandoned
Array ( [id] => 2672534 [patent_doc_number] => 04947372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-07 [patent_title] => 'Optical information memory medium for recording and erasing information' [patent_app_type] => 1 [patent_app_number] => 7/443860 [patent_app_country] => US [patent_app_date] => 1989-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 11753 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/947/04947372.pdf [firstpage_image] =>[orig_patent_app_number] => 443860 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/443860
Optical information memory medium for recording and erasing information Nov 29, 1989 Issued
07/440093 SIMICONDUCTOR INTEGRATED CIRCUIT WITH PLURAL PARALLEL LOAD ELEMENTS INTERCONNEECTED BETWEEN THE ENDS OF WIRING LAYER Nov 21, 1989 Abandoned
Array ( [id] => 2861807 [patent_doc_number] => 05134583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Nonvolatile semiconductor memory device having redundant data lines and page mode programming' [patent_app_type] => 1 [patent_app_number] => 7/440323 [patent_app_country] => US [patent_app_date] => 1989-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9028 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134583.pdf [firstpage_image] =>[orig_patent_app_number] => 440323 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/440323
Nonvolatile semiconductor memory device having redundant data lines and page mode programming Nov 21, 1989 Issued
Array ( [id] => 2682734 [patent_doc_number] => 05027321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Apparatus and method for improved reading/programming of virtual ground EPROM arrays' [patent_app_type] => 1 [patent_app_number] => 7/439694 [patent_app_country] => US [patent_app_date] => 1989-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4403 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/027/05027321.pdf [firstpage_image] =>[orig_patent_app_number] => 439694 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/439694
Apparatus and method for improved reading/programming of virtual ground EPROM arrays Nov 20, 1989 Issued
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