Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2881693 [patent_doc_number] => 05091881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Multiple port memory including merged bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/365664 [patent_app_country] => US [patent_app_date] => 1989-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6257 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091881.pdf [firstpage_image] =>[orig_patent_app_number] => 365664 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/365664
Multiple port memory including merged bipolar transistors Jun 12, 1989 Issued
Array ( [id] => 2703909 [patent_doc_number] => 05065362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Non-volatile RAM with integrated compact static RAM load configuration' [patent_app_type] => 1 [patent_app_number] => 7/361033 [patent_app_country] => US [patent_app_date] => 1989-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065362.pdf [firstpage_image] =>[orig_patent_app_number] => 361033 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/361033
Non-volatile RAM with integrated compact static RAM load configuration Jun 1, 1989 Issued
Array ( [id] => 2781457 [patent_doc_number] => RE034060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'High speed semiconductor memory device having a high gain sense amplifier' [patent_app_type] => 2 [patent_app_number] => 7/359684 [patent_app_country] => US [patent_app_date] => 1989-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9155 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/034/RE034060.pdf [firstpage_image] =>[orig_patent_app_number] => 359684 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/359684
High speed semiconductor memory device having a high gain sense amplifier May 30, 1989 Issued
07/358535 SEMICONDUCTOR MEMORY DEVICE HAVING SWITICHING CIRCUIT FOR COUPLING TOGETHER TWO PARIS OF BIT LINES May 29, 1989 Abandoned
Array ( [id] => 2633444 [patent_doc_number] => 04956816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'Non-volatile semiconductor memory having improved testing circuitry' [patent_app_type] => 1 [patent_app_number] => 7/358482 [patent_app_country] => US [patent_app_date] => 1989-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4295 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956816.pdf [firstpage_image] =>[orig_patent_app_number] => 358482 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/358482
Non-volatile semiconductor memory having improved testing circuitry May 29, 1989 Issued
07/342654 STATIC SEMICONDUCTOR MEMORY WITH READOUT INHIBIT MEANS Apr 23, 1989 Abandoned
07/341285 OPTICAL INFORMATION MEMORY MEDIUM AND METHODS AND APPARATUS FOR RECORDING AND ERASING INFORMATION Apr 20, 1989 Abandoned
Array ( [id] => 2678441 [patent_doc_number] => 04999813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-12 [patent_title] => 'Nonvolatile semiconductor memory having a stress test circuit' [patent_app_type] => 1 [patent_app_number] => 7/341287 [patent_app_country] => US [patent_app_date] => 1989-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3810 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/999/04999813.pdf [firstpage_image] =>[orig_patent_app_number] => 341287 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/341287
Nonvolatile semiconductor memory having a stress test circuit Apr 19, 1989 Issued
Array ( [id] => 3106975 [patent_doc_number] => 05313602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Multiprocessor system and method of control over order of transfer of data between buffer storages' [patent_app_type] => 1 [patent_app_number] => 7/340080 [patent_app_country] => US [patent_app_date] => 1989-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3032 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313602.pdf [firstpage_image] =>[orig_patent_app_number] => 340080 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/340080
Multiprocessor system and method of control over order of transfer of data between buffer storages Apr 17, 1989 Issued
07/337022 STORAGE MODULE AND ASSOCIATED METHOD FOR ACCESSING A DATA PROCESSING APPARATUS USING START AND STOP REFRESH ADDRESS Apr 11, 1989 Abandoned
Array ( [id] => 3007428 [patent_doc_number] => 05367654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Method and apparatus for controlling storage in computer system utilizing forecasted access requests and priority decision circuitry' [patent_app_type] => 1 [patent_app_number] => 7/337070 [patent_app_country] => US [patent_app_date] => 1989-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 10797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367654.pdf [firstpage_image] =>[orig_patent_app_number] => 337070 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/337070
Method and apparatus for controlling storage in computer system utilizing forecasted access requests and priority decision circuitry Apr 11, 1989 Issued
07/336522 SELF IDENTIFYING SCHEME FOR MEMORY Apr 9, 1989 Abandoned
Array ( [id] => 2817026 [patent_doc_number] => 05146577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Serial data circuit with randomly-accessed registers of different bit length' [patent_app_type] => 1 [patent_app_number] => 7/335391 [patent_app_country] => US [patent_app_date] => 1989-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3035 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146577.pdf [firstpage_image] =>[orig_patent_app_number] => 335391 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/335391
Serial data circuit with randomly-accessed registers of different bit length Apr 9, 1989 Issued
Array ( [id] => 2565102 [patent_doc_number] => 04961168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-02 [patent_title] => 'Bipolar-CMOS static random access memory device with bit line bias control' [patent_app_type] => 1 [patent_app_number] => 7/326755 [patent_app_country] => US [patent_app_date] => 1989-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2493 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/961/04961168.pdf [firstpage_image] =>[orig_patent_app_number] => 326755 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/326755
Bipolar-CMOS static random access memory device with bit line bias control Mar 20, 1989 Issued
Array ( [id] => 3590396 [patent_doc_number] => 05491807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'System and method for worm volume management of new and updated data files using variable threshold block addresses' [patent_app_type] => 1 [patent_app_number] => 7/325752 [patent_app_country] => US [patent_app_date] => 1989-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2061 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491807.pdf [firstpage_image] =>[orig_patent_app_number] => 325752 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/325752
System and method for worm volume management of new and updated data files using variable threshold block addresses Mar 19, 1989 Issued
Array ( [id] => 2532397 [patent_doc_number] => 04884237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-28 [patent_title] => 'Stacked double density memory module using industry standard memory chips' [patent_app_type] => 1 [patent_app_number] => 7/324958 [patent_app_country] => US [patent_app_date] => 1989-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2683 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/884/04884237.pdf [firstpage_image] =>[orig_patent_app_number] => 324958 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/324958
Stacked double density memory module using industry standard memory chips Mar 16, 1989 Issued
Array ( [id] => 2530972 [patent_doc_number] => 04881198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-14 [patent_title] => 'Duplicator in a magnetic bubble memory and process for duplicating bubbles therein' [patent_app_type] => 1 [patent_app_number] => 7/320860 [patent_app_country] => US [patent_app_date] => 1989-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 4355 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/881/04881198.pdf [firstpage_image] =>[orig_patent_app_number] => 320860 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/320860
Duplicator in a magnetic bubble memory and process for duplicating bubbles therein Mar 5, 1989 Issued
Array ( [id] => 2815648 [patent_doc_number] => 05115498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Local memory fast selecting apparatus including a memory management unit (MMU) and an auxiliary memory' [patent_app_type] => 1 [patent_app_number] => 7/315996 [patent_app_country] => US [patent_app_date] => 1989-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1894 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115498.pdf [firstpage_image] =>[orig_patent_app_number] => 315996 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/315996
Local memory fast selecting apparatus including a memory management unit (MMU) and an auxiliary memory Feb 26, 1989 Issued
07/308680 SEMICONDUCTOR CIRCUIT INCLUDING BIPOLAR AND FIELD-EFFECT TRANSISTORS DRIVING AN OUTPUT IN PARALLEL Feb 2, 1989 Abandoned
Array ( [id] => 2961580 [patent_doc_number] => 05222223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Method and apparatus for ordering and queueing multiple memory requests' [patent_app_type] => 1 [patent_app_number] => 7/306870 [patent_app_country] => US [patent_app_date] => 1989-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6061 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222223.pdf [firstpage_image] =>[orig_patent_app_number] => 306870 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/306870
Method and apparatus for ordering and queueing multiple memory requests Feb 2, 1989 Issued
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