| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1992-02-25
[patent_title] => 'Multiple port memory including merged bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 7/365664
[patent_app_country] => US
[patent_app_date] => 1989-06-13
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[firstpage_image] =>[orig_patent_app_number] => 365664
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/365664 | Multiple port memory including merged bipolar transistors | Jun 12, 1989 | Issued |
Array
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[patent_doc_number] => 05065362
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-12
[patent_title] => 'Non-volatile RAM with integrated compact static RAM load configuration'
[patent_app_type] => 1
[patent_app_number] => 7/361033
[patent_app_country] => US
[patent_app_date] => 1989-06-02
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[firstpage_image] =>[orig_patent_app_number] => 361033
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/361033 | Non-volatile RAM with integrated compact static RAM load configuration | Jun 1, 1989 | Issued |
Array
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[id] => 2781457
[patent_doc_number] => RE034060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-08
[patent_title] => 'High speed semiconductor memory device having a high gain sense amplifier'
[patent_app_type] => 2
[patent_app_number] => 7/359684
[patent_app_country] => US
[patent_app_date] => 1989-05-31
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[firstpage_image] =>[orig_patent_app_number] => 359684
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/359684 | High speed semiconductor memory device having a high gain sense amplifier | May 30, 1989 | Issued |
| 07/358535 | SEMICONDUCTOR MEMORY DEVICE HAVING SWITICHING CIRCUIT FOR COUPLING TOGETHER TWO PARIS OF BIT LINES | May 29, 1989 | Abandoned |
Array
(
[id] => 2633444
[patent_doc_number] => 04956816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Non-volatile semiconductor memory having improved testing circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/358482
[patent_app_country] => US
[patent_app_date] => 1989-05-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/956/04956816.pdf
[firstpage_image] =>[orig_patent_app_number] => 358482
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/358482 | Non-volatile semiconductor memory having improved testing circuitry | May 29, 1989 | Issued |
| 07/342654 | STATIC SEMICONDUCTOR MEMORY WITH READOUT INHIBIT MEANS | Apr 23, 1989 | Abandoned |
| 07/341285 | OPTICAL INFORMATION MEMORY MEDIUM AND METHODS AND APPARATUS FOR RECORDING AND ERASING INFORMATION | Apr 20, 1989 | Abandoned |
Array
(
[id] => 2678441
[patent_doc_number] => 04999813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-12
[patent_title] => 'Nonvolatile semiconductor memory having a stress test circuit'
[patent_app_type] => 1
[patent_app_number] => 7/341287
[patent_app_country] => US
[patent_app_date] => 1989-04-20
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[firstpage_image] =>[orig_patent_app_number] => 341287
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/341287 | Nonvolatile semiconductor memory having a stress test circuit | Apr 19, 1989 | Issued |
Array
(
[id] => 3106975
[patent_doc_number] => 05313602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Multiprocessor system and method of control over order of transfer of data between buffer storages'
[patent_app_type] => 1
[patent_app_number] => 7/340080
[patent_app_country] => US
[patent_app_date] => 1989-04-18
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[firstpage_image] =>[orig_patent_app_number] => 340080
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/340080 | Multiprocessor system and method of control over order of transfer of data between buffer storages | Apr 17, 1989 | Issued |
| 07/337022 | STORAGE MODULE AND ASSOCIATED METHOD FOR ACCESSING A DATA PROCESSING APPARATUS USING START AND STOP REFRESH ADDRESS | Apr 11, 1989 | Abandoned |
Array
(
[id] => 3007428
[patent_doc_number] => 05367654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Method and apparatus for controlling storage in computer system utilizing forecasted access requests and priority decision circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/337070
[patent_app_country] => US
[patent_app_date] => 1989-04-12
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[pdf_file] => patents/05/367/05367654.pdf
[firstpage_image] =>[orig_patent_app_number] => 337070
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/337070 | Method and apparatus for controlling storage in computer system utilizing forecasted access requests and priority decision circuitry | Apr 11, 1989 | Issued |
| 07/336522 | SELF IDENTIFYING SCHEME FOR MEMORY | Apr 9, 1989 | Abandoned |
Array
(
[id] => 2817026
[patent_doc_number] => 05146577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-08
[patent_title] => 'Serial data circuit with randomly-accessed registers of different bit length'
[patent_app_type] => 1
[patent_app_number] => 7/335391
[patent_app_country] => US
[patent_app_date] => 1989-04-10
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[firstpage_image] =>[orig_patent_app_number] => 335391
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/335391 | Serial data circuit with randomly-accessed registers of different bit length | Apr 9, 1989 | Issued |
Array
(
[id] => 2565102
[patent_doc_number] => 04961168
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-02
[patent_title] => 'Bipolar-CMOS static random access memory device with bit line bias control'
[patent_app_type] => 1
[patent_app_number] => 7/326755
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/326755 | Bipolar-CMOS static random access memory device with bit line bias control | Mar 20, 1989 | Issued |
Array
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[id] => 3590396
[patent_doc_number] => 05491807
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[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'System and method for worm volume management of new and updated data files using variable threshold block addresses'
[patent_app_type] => 1
[patent_app_number] => 7/325752
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[patent_app_date] => 1989-03-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/325752 | System and method for worm volume management of new and updated data files using variable threshold block addresses | Mar 19, 1989 | Issued |
Array
(
[id] => 2532397
[patent_doc_number] => 04884237
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[patent_issue_date] => 1989-11-28
[patent_title] => 'Stacked double density memory module using industry standard memory chips'
[patent_app_type] => 1
[patent_app_number] => 7/324958
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[firstpage_image] =>[orig_patent_app_number] => 324958
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/324958 | Stacked double density memory module using industry standard memory chips | Mar 16, 1989 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1989-11-14
[patent_title] => 'Duplicator in a magnetic bubble memory and process for duplicating bubbles therein'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/320860 | Duplicator in a magnetic bubble memory and process for duplicating bubbles therein | Mar 5, 1989 | Issued |
Array
(
[id] => 2815648
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-19
[patent_title] => 'Local memory fast selecting apparatus including a memory management unit (MMU) and an auxiliary memory'
[patent_app_type] => 1
[patent_app_number] => 7/315996
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/315996 | Local memory fast selecting apparatus including a memory management unit (MMU) and an auxiliary memory | Feb 26, 1989 | Issued |
| 07/308680 | SEMICONDUCTOR CIRCUIT INCLUDING BIPOLAR AND FIELD-EFFECT TRANSISTORS DRIVING AN OUTPUT IN PARALLEL | Feb 2, 1989 | Abandoned |
Array
(
[id] => 2961580
[patent_doc_number] => 05222223
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[patent_kind] => NA
[patent_issue_date] => 1993-06-22
[patent_title] => 'Method and apparatus for ordering and queueing multiple memory requests'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/306870 | Method and apparatus for ordering and queueing multiple memory requests | Feb 2, 1989 | Issued |