| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2840417
[patent_doc_number] => 05099451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-24
[patent_title] => 'Memory array with electrically programmable memory cells and electricaly unprogrammable, unerasable memory cells, both types of memory cells having floating gate transistors'
[patent_app_type] => 1
[patent_app_number] => 7/272123
[patent_app_country] => US
[patent_app_date] => 1988-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 5291
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/099/05099451.pdf
[firstpage_image] =>[orig_patent_app_number] => 272123
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/272123 | Memory array with electrically programmable memory cells and electricaly unprogrammable, unerasable memory cells, both types of memory cells having floating gate transistors | Nov 15, 1988 | Issued |
Array
(
[id] => 3092115
[patent_doc_number] => 05280448
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Dynamic memory with group bit lines and associated bit line group selector'
[patent_app_type] => 1
[patent_app_number] => 7/271913
[patent_app_country] => US
[patent_app_date] => 1988-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4158
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/280/05280448.pdf
[firstpage_image] =>[orig_patent_app_number] => 271913
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/271913 | Dynamic memory with group bit lines and associated bit line group selector | Nov 15, 1988 | Issued |
| 07/269353 | FIELD MEMORY SELF-REFRESHING DEVICE UTILIZING A REFRESH CLOCK SIGNAL FROM TWO SEPARATE CLOCK SIGNALS | Nov 9, 1988 | Abandoned |
| 07/269197 | APPARATUS FOR PAGE MODE PROGRAMMING OF AN EEPROM CELL ARRAY WITH FALSE LOADING PROTECTION | Nov 8, 1988 | Abandoned |
Array
(
[id] => 2607146
[patent_doc_number] => 04924438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-08
[patent_title] => 'Non-volatile semiconductor memory including a high voltage switching circuit'
[patent_app_type] => 1
[patent_app_number] => 7/268607
[patent_app_country] => US
[patent_app_date] => 1988-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 3702
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/924/04924438.pdf
[firstpage_image] =>[orig_patent_app_number] => 268607
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/268607 | Non-volatile semiconductor memory including a high voltage switching circuit | Nov 6, 1988 | Issued |
| 07/265384 | FERROELECTRIC MEMORY WITH DIODE ISOLATION | Oct 30, 1988 | Abandoned |
| 07/264404 | DECODING GLOBAL DRIVE/BOOT SIGNALS USING LOCAL PREDECODERS | Oct 27, 1988 | Abandoned |
Array
(
[id] => 2604187
[patent_doc_number] => 04933908
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-12
[patent_title] => 'Fault detection in memory refreshing system'
[patent_app_type] => 1
[patent_app_number] => 7/264113
[patent_app_country] => US
[patent_app_date] => 1988-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2528
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/933/04933908.pdf
[firstpage_image] =>[orig_patent_app_number] => 264113
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/264113 | Fault detection in memory refreshing system | Oct 27, 1988 | Issued |
| 07/261863 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A STRESS TEST CIRCUIT | Oct 24, 1988 | Abandoned |
Array
(
[id] => 2677907
[patent_doc_number] => 04905197
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-27
[patent_title] => 'Semiconductor memory having circuitry for discharging a digit line before verifying operation'
[patent_app_type] => 1
[patent_app_number] => 7/262227
[patent_app_country] => US
[patent_app_date] => 1988-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4866
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/905/04905197.pdf
[firstpage_image] =>[orig_patent_app_number] => 262227
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/262227 | Semiconductor memory having circuitry for discharging a digit line before verifying operation | Oct 20, 1988 | Issued |
Array
(
[id] => 2634098
[patent_doc_number] => 04920515
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-24
[patent_title] => 'Programmable logic array having an improved testing arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/259884
[patent_app_country] => US
[patent_app_date] => 1988-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3207
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/920/04920515.pdf
[firstpage_image] =>[orig_patent_app_number] => 259884
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/259884 | Programmable logic array having an improved testing arrangement | Oct 18, 1988 | Issued |
Array
(
[id] => 2904160
[patent_doc_number] => 05177708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-05
[patent_title] => 'Dynamic random access memory and method for equalizing sense amplifier drive signal lines'
[patent_app_type] => 1
[patent_app_number] => 7/260132
[patent_app_country] => US
[patent_app_date] => 1988-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3455
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 348
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/177/05177708.pdf
[firstpage_image] =>[orig_patent_app_number] => 260132
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/260132 | Dynamic random access memory and method for equalizing sense amplifier drive signal lines | Oct 18, 1988 | Issued |
| 07/258684 | ADDRESS DETECTION CIRCUIT USING A MEMORY | Oct 16, 1988 | Abandoned |
| 07/258813 | TESTING ARRANGEMENT FOR A COMBINATION LOGIC BLOCK AND MEMORY CIRCUIT | Oct 16, 1988 | Abandoned |
| 07/253181 | MEMORY DEVICE WITH IMPROVED COMMON DATA LINE BIAS ARRANGEMENT | Oct 3, 1988 | Abandoned |
Array
(
[id] => 2607221
[patent_doc_number] => 04924442
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-08
[patent_title] => 'Pull up circuit for digit lines in a semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 7/252494
[patent_app_country] => US
[patent_app_date] => 1988-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4619
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/924/04924442.pdf
[firstpage_image] =>[orig_patent_app_number] => 252494
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/252494 | Pull up circuit for digit lines in a semiconductor memory | Sep 29, 1988 | Issued |
Array
(
[id] => 2647379
[patent_doc_number] => 04914631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-03
[patent_title] => 'Pull up circuit for sense lines in a semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 7/252585
[patent_app_country] => US
[patent_app_date] => 1988-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4638
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/914/04914631.pdf
[firstpage_image] =>[orig_patent_app_number] => 252585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/252585 | Pull up circuit for sense lines in a semiconductor memory | Sep 29, 1988 | Issued |
Array
(
[id] => 2633480
[patent_doc_number] => 04956818
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Memory incorporating logic LSI and method for testing the same LSI'
[patent_app_type] => 1
[patent_app_number] => 7/251913
[patent_app_country] => US
[patent_app_date] => 1988-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3671
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/956/04956818.pdf
[firstpage_image] =>[orig_patent_app_number] => 251913
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/251913 | Memory incorporating logic LSI and method for testing the same LSI | Sep 29, 1988 | Issued |
| 07/249903 | SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT LATCHES FOR IMPROVED MERGING OF OUTPUT DATA | Sep 26, 1988 | Abandoned |
Array
(
[id] => 2678450
[patent_doc_number] => 04954994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-04
[patent_title] => 'FIFO memory capable of simultaneously selecting a plurality of word lines'
[patent_app_type] => 1
[patent_app_number] => 7/245833
[patent_app_country] => US
[patent_app_date] => 1988-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3518
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/954/04954994.pdf
[firstpage_image] =>[orig_patent_app_number] => 245833
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/245833 | FIFO memory capable of simultaneously selecting a plurality of word lines | Sep 15, 1988 | Issued |
