| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 1989-10-10
[patent_title] => 'Dual storage cell memory including data transfer circuits'
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[patent_app_number] => 7/203424
[patent_app_country] => US
[patent_app_date] => 1988-06-07
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Array
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[patent_doc_number] => 04945514
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-31
[patent_title] => 'Method of bistable optical information storage using antiferroelectric phase PLZT ceramics'
[patent_app_type] => 1
[patent_app_number] => 7/200104
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[firstpage_image] =>[orig_patent_app_number] => 200104
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/200104 | Method of bistable optical information storage using antiferroelectric phase PLZT ceramics | May 30, 1988 | Issued |
Array
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[id] => 2595428
[patent_doc_number] => 04908796
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-13
[patent_title] => 'Registered outputs for a memory device'
[patent_app_type] => 1
[patent_app_number] => 7/198164
[patent_app_country] => US
[patent_app_date] => 1988-05-24
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[firstpage_image] =>[orig_patent_app_number] => 198164
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/198164 | Registered outputs for a memory device | May 23, 1988 | Issued |
Array
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[patent_doc_number] => 04972348
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-20
[patent_title] => 'Opto-electric hybrid associative memory'
[patent_app_type] => 1
[patent_app_number] => 7/196644
[patent_app_country] => US
[patent_app_date] => 1988-05-20
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[firstpage_image] =>[orig_patent_app_number] => 196644
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/196644 | Opto-electric hybrid associative memory | May 19, 1988 | Issued |
Array
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[patent_doc_number] => 04914630
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-03
[patent_title] => 'Refresh arrangement in a block divided memory including a plurality of shift registers'
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[patent_app_number] => 7/192714
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[patent_app_date] => 1988-05-11
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[firstpage_image] =>[orig_patent_app_number] => 192714
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/192714 | Refresh arrangement in a block divided memory including a plurality of shift registers | May 10, 1988 | Issued |
Array
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[id] => 2742156
[patent_doc_number] => 04998220
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[patent_issue_date] => 1991-03-05
[patent_title] => 'EEPROM with improved erase structure'
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[patent_app_number] => 7/189874
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[firstpage_image] =>[orig_patent_app_number] => 189874
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/189874 | EEPROM with improved erase structure | May 2, 1988 | Issued |
Array
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[patent_doc_number] => 04868790
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[patent_kind] => NA
[patent_issue_date] => 1989-09-19
[patent_title] => 'Reference circuit for integrated memory arrays having virtual ground connections'
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[patent_app_number] => 7/187134
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[pdf_file] => patents/04/868/04868790.pdf
[firstpage_image] =>[orig_patent_app_number] => 187134
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/187134 | Reference circuit for integrated memory arrays having virtual ground connections | Apr 27, 1988 | Issued |
Array
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[id] => 2538442
[patent_doc_number] => 04862412
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-29
[patent_title] => 'Content-addressable memory having control circuitry and independent controls for match and write cycles'
[patent_app_type] => 1
[patent_app_number] => 7/185624
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[patent_app_date] => 1988-04-25
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[pdf_file] => patents/04/862/04862412.pdf
[firstpage_image] =>[orig_patent_app_number] => 185624
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/185624 | Content-addressable memory having control circuitry and independent controls for match and write cycles | Apr 24, 1988 | Issued |
Array
(
[id] => 2532890
[patent_doc_number] => 04873663
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-10
[patent_title] => 'Control memory using recirculating shift registers for a TDM switching apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/185653
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[patent_app_date] => 1988-04-25
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[firstpage_image] =>[orig_patent_app_number] => 185653
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/185653 | Control memory using recirculating shift registers for a TDM switching apparatus | Apr 24, 1988 | Issued |
| 07/184814 | PROGRAMMABLE SEMICONDUCTOR MEMORY INCLEDING SERIES CONNECTED MEMORY CELLS | Apr 21, 1988 | Abandoned |
Array
(
[id] => 2594962
[patent_doc_number] => 04891793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-02
[patent_title] => 'Discharge circuit for a semiconductor memory including address transition detectors'
[patent_app_type] => 1
[patent_app_number] => 7/183713
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[patent_app_date] => 1988-04-19
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[firstpage_image] =>[orig_patent_app_number] => 183713
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/183713 | Discharge circuit for a semiconductor memory including address transition detectors | Apr 18, 1988 | Issued |
Array
(
[id] => 2531104
[patent_doc_number] => 04881205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-11-14
[patent_title] => 'Compact electronic apparatus with a refresh unit for a dynamic type memory'
[patent_app_type] => 1
[patent_app_number] => 7/181444
[patent_app_country] => US
[patent_app_date] => 1988-04-14
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[pdf_file] => patents/04/881/04881205.pdf
[firstpage_image] =>[orig_patent_app_number] => 181444
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/181444 | Compact electronic apparatus with a refresh unit for a dynamic type memory | Apr 13, 1988 | Issued |
| 07/179464 | COMPUTER SYSTEM WITH DISTRIBUTED ASSOCIATIVE MEMORY | Apr 7, 1988 | Abandoned |
Array
(
[id] => 2538459
[patent_doc_number] => 04862413
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[patent_issue_date] => 1989-08-29
[patent_title] => 'Semiconductor ROM with reduced supply voltage requirement'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/180648 | Semiconductor ROM with reduced supply voltage requirement | Apr 3, 1988 | Issued |
Array
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[id] => 2529993
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[patent_issue_date] => 1989-12-05
[patent_title] => 'Memory device and method implementing wordline redundancy without an access time penalty'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/176473 | Memory device and method implementing wordline redundancy without an access time penalty | Mar 31, 1988 | Issued |
Array
(
[id] => 2759885
[patent_doc_number] => 05022006
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[patent_kind] => NA
[patent_issue_date] => 1991-06-04
[patent_title] => 'Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells'
[patent_app_type] => 1
[patent_app_number] => 7/175883
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[patent_app_date] => 1988-04-01
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[firstpage_image] =>[orig_patent_app_number] => 175883
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/175883 | Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells | Mar 31, 1988 | Issued |
| 07/174893 | SEMICONDUCTOR MEMORY DEVICE | Mar 28, 1988 | Abandoned |
| 07/173005 | PROGRAMMABLE MEMORY CELL STRUCTURE AND MANUFACTURING METHOD | Mar 27, 1988 | Abandoned |
Array
(
[id] => 2643406
[patent_doc_number] => 04893275
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[patent_kind] => NA
[patent_issue_date] => 1990-01-09
[patent_title] => 'High voltage switching circuit in a nonvolatile memory'
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[patent_app_date] => 1988-03-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/173563 | High voltage switching circuit in a nonvolatile memory | Mar 24, 1988 | Issued |
Array
(
[id] => 2494976
[patent_doc_number] => 04866676
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-12
[patent_title] => 'Testing arrangement for a DRAM with redundancy'
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[patent_app_country] => US
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