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Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2532925 [patent_doc_number] => 04873665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Dual storage cell memory including data transfer circuits' [patent_app_type] => 1 [patent_app_number] => 7/203424 [patent_app_country] => US [patent_app_date] => 1988-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3260 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873665.pdf [firstpage_image] =>[orig_patent_app_number] => 203424 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/203424
Dual storage cell memory including data transfer circuits Jun 6, 1988 Issued
Array ( [id] => 2572324 [patent_doc_number] => 04945514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-31 [patent_title] => 'Method of bistable optical information storage using antiferroelectric phase PLZT ceramics' [patent_app_type] => 1 [patent_app_number] => 7/200104 [patent_app_country] => US [patent_app_date] => 1988-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2718 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/945/04945514.pdf [firstpage_image] =>[orig_patent_app_number] => 200104 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/200104
Method of bistable optical information storage using antiferroelectric phase PLZT ceramics May 30, 1988 Issued
Array ( [id] => 2595428 [patent_doc_number] => 04908796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-13 [patent_title] => 'Registered outputs for a memory device' [patent_app_type] => 1 [patent_app_number] => 7/198164 [patent_app_country] => US [patent_app_date] => 1988-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/908/04908796.pdf [firstpage_image] =>[orig_patent_app_number] => 198164 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/198164
Registered outputs for a memory device May 23, 1988 Issued
Array ( [id] => 2664322 [patent_doc_number] => 04972348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Opto-electric hybrid associative memory' [patent_app_type] => 1 [patent_app_number] => 7/196644 [patent_app_country] => US [patent_app_date] => 1988-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3855 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/972/04972348.pdf [firstpage_image] =>[orig_patent_app_number] => 196644 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/196644
Opto-electric hybrid associative memory May 19, 1988 Issued
Array ( [id] => 2647361 [patent_doc_number] => 04914630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-03 [patent_title] => 'Refresh arrangement in a block divided memory including a plurality of shift registers' [patent_app_type] => 1 [patent_app_number] => 7/192714 [patent_app_country] => US [patent_app_date] => 1988-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4934 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/914/04914630.pdf [firstpage_image] =>[orig_patent_app_number] => 192714 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/192714
Refresh arrangement in a block divided memory including a plurality of shift registers May 10, 1988 Issued
Array ( [id] => 2742156 [patent_doc_number] => 04998220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'EEPROM with improved erase structure' [patent_app_type] => 1 [patent_app_number] => 7/189874 [patent_app_country] => US [patent_app_date] => 1988-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 8399 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/998/04998220.pdf [firstpage_image] =>[orig_patent_app_number] => 189874 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/189874
EEPROM with improved erase structure May 2, 1988 Issued
Array ( [id] => 2498942 [patent_doc_number] => 04868790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Reference circuit for integrated memory arrays having virtual ground connections' [patent_app_type] => 1 [patent_app_number] => 7/187134 [patent_app_country] => US [patent_app_date] => 1988-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1965 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868790.pdf [firstpage_image] =>[orig_patent_app_number] => 187134 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/187134
Reference circuit for integrated memory arrays having virtual ground connections Apr 27, 1988 Issued
Array ( [id] => 2538442 [patent_doc_number] => 04862412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-29 [patent_title] => 'Content-addressable memory having control circuitry and independent controls for match and write cycles' [patent_app_type] => 1 [patent_app_number] => 7/185624 [patent_app_country] => US [patent_app_date] => 1988-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4538 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/862/04862412.pdf [firstpage_image] =>[orig_patent_app_number] => 185624 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/185624
Content-addressable memory having control circuitry and independent controls for match and write cycles Apr 24, 1988 Issued
Array ( [id] => 2532890 [patent_doc_number] => 04873663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Control memory using recirculating shift registers for a TDM switching apparatus' [patent_app_type] => 1 [patent_app_number] => 7/185653 [patent_app_country] => US [patent_app_date] => 1988-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2153 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873663.pdf [firstpage_image] =>[orig_patent_app_number] => 185653 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/185653
Control memory using recirculating shift registers for a TDM switching apparatus Apr 24, 1988 Issued
07/184814 PROGRAMMABLE SEMICONDUCTOR MEMORY INCLEDING SERIES CONNECTED MEMORY CELLS Apr 21, 1988 Abandoned
Array ( [id] => 2594962 [patent_doc_number] => 04891793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-02 [patent_title] => 'Discharge circuit for a semiconductor memory including address transition detectors' [patent_app_type] => 1 [patent_app_number] => 7/183713 [patent_app_country] => US [patent_app_date] => 1988-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3157 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/891/04891793.pdf [firstpage_image] =>[orig_patent_app_number] => 183713 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/183713
Discharge circuit for a semiconductor memory including address transition detectors Apr 18, 1988 Issued
Array ( [id] => 2531104 [patent_doc_number] => 04881205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-14 [patent_title] => 'Compact electronic apparatus with a refresh unit for a dynamic type memory' [patent_app_type] => 1 [patent_app_number] => 7/181444 [patent_app_country] => US [patent_app_date] => 1988-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6116 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/881/04881205.pdf [firstpage_image] =>[orig_patent_app_number] => 181444 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/181444
Compact electronic apparatus with a refresh unit for a dynamic type memory Apr 13, 1988 Issued
07/179464 COMPUTER SYSTEM WITH DISTRIBUTED ASSOCIATIVE MEMORY Apr 7, 1988 Abandoned
Array ( [id] => 2538459 [patent_doc_number] => 04862413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-29 [patent_title] => 'Semiconductor ROM with reduced supply voltage requirement' [patent_app_type] => 1 [patent_app_number] => 7/180648 [patent_app_country] => US [patent_app_date] => 1988-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4991 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 617 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/862/04862413.pdf [firstpage_image] =>[orig_patent_app_number] => 180648 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/180648
Semiconductor ROM with reduced supply voltage requirement Apr 3, 1988 Issued
Array ( [id] => 2529993 [patent_doc_number] => 04885720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-05 [patent_title] => 'Memory device and method implementing wordline redundancy without an access time penalty' [patent_app_type] => 1 [patent_app_number] => 7/176473 [patent_app_country] => US [patent_app_date] => 1988-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 5744 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/885/04885720.pdf [firstpage_image] =>[orig_patent_app_number] => 176473 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/176473
Memory device and method implementing wordline redundancy without an access time penalty Mar 31, 1988 Issued
Array ( [id] => 2759885 [patent_doc_number] => 05022006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells' [patent_app_type] => 1 [patent_app_number] => 7/175883 [patent_app_country] => US [patent_app_date] => 1988-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4447 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/022/05022006.pdf [firstpage_image] =>[orig_patent_app_number] => 175883 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/175883
Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells Mar 31, 1988 Issued
07/174893 SEMICONDUCTOR MEMORY DEVICE Mar 28, 1988 Abandoned
07/173005 PROGRAMMABLE MEMORY CELL STRUCTURE AND MANUFACTURING METHOD Mar 27, 1988 Abandoned
Array ( [id] => 2643406 [patent_doc_number] => 04893275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-09 [patent_title] => 'High voltage switching circuit in a nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 7/173563 [patent_app_country] => US [patent_app_date] => 1988-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2115 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/893/04893275.pdf [firstpage_image] =>[orig_patent_app_number] => 173563 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/173563
High voltage switching circuit in a nonvolatile memory Mar 24, 1988 Issued
Array ( [id] => 2494976 [patent_doc_number] => 04866676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-12 [patent_title] => 'Testing arrangement for a DRAM with redundancy' [patent_app_type] => 1 [patent_app_number] => 7/172514 [patent_app_country] => US [patent_app_date] => 1988-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2948 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/866/04866676.pdf [firstpage_image] =>[orig_patent_app_number] => 172514 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/172514
Testing arrangement for a DRAM with redundancy Mar 23, 1988 Issued
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