Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2602605 [patent_doc_number] => 04918657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-17 [patent_title] => 'Semiconductor memory device provided with an improved precharge and enable control circuit' [patent_app_type] => 1 [patent_app_number] => 7/169683 [patent_app_country] => US [patent_app_date] => 1988-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3672 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/918/04918657.pdf [firstpage_image] =>[orig_patent_app_number] => 169683 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/169683
Semiconductor memory device provided with an improved precharge and enable control circuit Mar 17, 1988 Issued
Array ( [id] => 2572678 [patent_doc_number] => 04849937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'Digital delay unit with interleaved memory' [patent_app_type] => 1 [patent_app_number] => 7/169066 [patent_app_country] => US [patent_app_date] => 1988-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5127 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849937.pdf [firstpage_image] =>[orig_patent_app_number] => 169066 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/169066
Digital delay unit with interleaved memory Mar 16, 1988 Issued
Array ( [id] => 2633501 [patent_doc_number] => 04956819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'Circuit configuration and a method of testing storage cells' [patent_app_type] => 1 [patent_app_number] => 7/168653 [patent_app_country] => US [patent_app_date] => 1988-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4670 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956819.pdf [firstpage_image] =>[orig_patent_app_number] => 168653 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/168653
Circuit configuration and a method of testing storage cells Mar 15, 1988 Issued
07/167174 BI-CMOS SEMICONDUCTOR MEMORY DEVICE Mar 10, 1988 Abandoned
Array ( [id] => 2669022 [patent_doc_number] => 05070070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-03 [patent_title] => 'High temperature superconducting memory storage device and cryotron' [patent_app_type] => 1 [patent_app_number] => 7/165683 [patent_app_country] => US [patent_app_date] => 1988-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5186 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/070/05070070.pdf [firstpage_image] =>[orig_patent_app_number] => 165683 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/165683
High temperature superconducting memory storage device and cryotron Mar 8, 1988 Issued
Array ( [id] => 2558215 [patent_doc_number] => 04811292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-07 [patent_title] => 'Semiconductor memory in which data readout operation is carried out over wide power voltage range' [patent_app_type] => 1 [patent_app_number] => 7/166743 [patent_app_country] => US [patent_app_date] => 1988-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4362 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/811/04811292.pdf [firstpage_image] =>[orig_patent_app_number] => 166743 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/166743
Semiconductor memory in which data readout operation is carried out over wide power voltage range Mar 1, 1988 Issued
07/154509 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE Feb 4, 1988 Abandoned
Array ( [id] => 2644785 [patent_doc_number] => 04899317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-06 [patent_title] => 'Bit line precharge in a bimos ram' [patent_app_type] => 1 [patent_app_number] => 7/151044 [patent_app_country] => US [patent_app_date] => 1988-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3642 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/899/04899317.pdf [firstpage_image] =>[orig_patent_app_number] => 151044 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/151044
Bit line precharge in a bimos ram Jan 31, 1988 Issued
Array ( [id] => 2608189 [patent_doc_number] => 04922453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Bit line structure of dynamic type semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/150373 [patent_app_country] => US [patent_app_date] => 1988-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/922/04922453.pdf [firstpage_image] =>[orig_patent_app_number] => 150373 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/150373
Bit line structure of dynamic type semiconductor memory device Jan 28, 1988 Issued
07/149373 PROGRAMMABLE MEMORY DATA PROTECTION SCHEME Jan 27, 1988 Abandoned
07/140243 A SEMICONDUCTOR MEMORY HAVING A POLYCRYSTALLINE SILICON LOAD RESISTOR AND CMOS PERIPHERAL CIRCUITRY Dec 30, 1987 Abandoned
Array ( [id] => 2604111 [patent_doc_number] => 04933904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-12 [patent_title] => 'Dense EPROM having serially coupled floating gate transistors' [patent_app_type] => 1 [patent_app_number] => 7/134585 [patent_app_country] => US [patent_app_date] => 1987-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2927 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/933/04933904.pdf [firstpage_image] =>[orig_patent_app_number] => 134585 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/134585
Dense EPROM having serially coupled floating gate transistors Dec 13, 1987 Issued
Array ( [id] => 2491268 [patent_doc_number] => 04823314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Integrated circuit dual port static memory cell' [patent_app_type] => 1 [patent_app_number] => 7/132416 [patent_app_country] => US [patent_app_date] => 1987-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2937 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823314.pdf [firstpage_image] =>[orig_patent_app_number] => 132416 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/132416
Integrated circuit dual port static memory cell Dec 13, 1987 Issued
07/131633 BIT LINE STRUCTURE FOR SEMICONDUCTOR MEMORY DEVICE Dec 10, 1987 Abandoned
Array ( [id] => 2607128 [patent_doc_number] => 04924437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Erasable programmable memory including buried diffusion source/drain lines and erase lines' [patent_app_type] => 1 [patent_app_number] => 7/130774 [patent_app_country] => US [patent_app_date] => 1987-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7049 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/924/04924437.pdf [firstpage_image] =>[orig_patent_app_number] => 130774 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/130774
Erasable programmable memory including buried diffusion source/drain lines and erase lines Dec 8, 1987 Issued
Array ( [id] => 2643538 [patent_doc_number] => 04893282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/133153 [patent_app_country] => US [patent_app_date] => 1987-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 2118 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/893/04893282.pdf [firstpage_image] =>[orig_patent_app_number] => 133153 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/133153
Semiconductor memory device Dec 6, 1987 Issued
Array ( [id] => 2493007 [patent_doc_number] => 04800528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-24 [patent_title] => 'Non-volatile memory having charge correction circuitry' [patent_app_type] => 1 [patent_app_number] => 7/129930 [patent_app_country] => US [patent_app_date] => 1987-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 11695 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/800/04800528.pdf [firstpage_image] =>[orig_patent_app_number] => 129930 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/129930
Non-volatile memory having charge correction circuitry Dec 2, 1987 Issued
Array ( [id] => 2678404 [patent_doc_number] => 04999811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-12 [patent_title] => 'Trench DRAM cell with dynamic gain' [patent_app_type] => 1 [patent_app_number] => 7/126523 [patent_app_country] => US [patent_app_date] => 1987-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4792 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/999/04999811.pdf [firstpage_image] =>[orig_patent_app_number] => 126523 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/126523
Trench DRAM cell with dynamic gain Nov 29, 1987 Issued
Array ( [id] => 2525099 [patent_doc_number] => 04875192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-17 [patent_title] => 'Semiconductor memory with an improved nibble mode arrangement' [patent_app_type] => 1 [patent_app_number] => 7/127621 [patent_app_country] => US [patent_app_date] => 1987-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 7197 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/875/04875192.pdf [firstpage_image] =>[orig_patent_app_number] => 127621 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/127621
Semiconductor memory with an improved nibble mode arrangement Nov 29, 1987 Issued
Array ( [id] => 2568120 [patent_doc_number] => 04853895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-01 [patent_title] => 'EEPROM including programming electrode extending through the control gate electrode' [patent_app_type] => 1 [patent_app_number] => 7/126443 [patent_app_country] => US [patent_app_date] => 1987-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4433 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/853/04853895.pdf [firstpage_image] =>[orig_patent_app_number] => 126443 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/126443
EEPROM including programming electrode extending through the control gate electrode Nov 29, 1987 Issued
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