| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_title] => 'Semiconductor memory device provided with an improved precharge and enable control circuit'
[patent_app_type] => 1
[patent_app_number] => 7/169683
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Array
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[patent_doc_number] => 04849937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-18
[patent_title] => 'Digital delay unit with interleaved memory'
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[patent_app_number] => 7/169066
[patent_app_country] => US
[patent_app_date] => 1988-03-17
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[firstpage_image] =>[orig_patent_app_number] => 169066
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/169066 | Digital delay unit with interleaved memory | Mar 16, 1988 | Issued |
Array
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[id] => 2633501
[patent_doc_number] => 04956819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Circuit configuration and a method of testing storage cells'
[patent_app_type] => 1
[patent_app_number] => 7/168653
[patent_app_country] => US
[patent_app_date] => 1988-03-16
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[pdf_file] => patents/04/956/04956819.pdf
[firstpage_image] =>[orig_patent_app_number] => 168653
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/168653 | Circuit configuration and a method of testing storage cells | Mar 15, 1988 | Issued |
| 07/167174 | BI-CMOS SEMICONDUCTOR MEMORY DEVICE | Mar 10, 1988 | Abandoned |
Array
(
[id] => 2669022
[patent_doc_number] => 05070070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'High temperature superconducting memory storage device and cryotron'
[patent_app_type] => 1
[patent_app_number] => 7/165683
[patent_app_country] => US
[patent_app_date] => 1988-03-09
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[pdf_file] => patents/05/070/05070070.pdf
[firstpage_image] =>[orig_patent_app_number] => 165683
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/165683 | High temperature superconducting memory storage device and cryotron | Mar 8, 1988 | Issued |
Array
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[id] => 2558215
[patent_doc_number] => 04811292
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-03-07
[patent_title] => 'Semiconductor memory in which data readout operation is carried out over wide power voltage range'
[patent_app_type] => 1
[patent_app_number] => 7/166743
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[patent_app_date] => 1988-03-02
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[firstpage_image] =>[orig_patent_app_number] => 166743
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/166743 | Semiconductor memory in which data readout operation is carried out over wide power voltage range | Mar 1, 1988 | Issued |
| 07/154509 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE | Feb 4, 1988 | Abandoned |
Array
(
[id] => 2644785
[patent_doc_number] => 04899317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-06
[patent_title] => 'Bit line precharge in a bimos ram'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/151044 | Bit line precharge in a bimos ram | Jan 31, 1988 | Issued |
Array
(
[id] => 2608189
[patent_doc_number] => 04922453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-01
[patent_title] => 'Bit line structure of dynamic type semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/150373
[patent_app_country] => US
[patent_app_date] => 1988-01-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/922/04922453.pdf
[firstpage_image] =>[orig_patent_app_number] => 150373
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/150373 | Bit line structure of dynamic type semiconductor memory device | Jan 28, 1988 | Issued |
| 07/149373 | PROGRAMMABLE MEMORY DATA PROTECTION SCHEME | Jan 27, 1988 | Abandoned |
| 07/140243 | A SEMICONDUCTOR MEMORY HAVING A POLYCRYSTALLINE SILICON LOAD RESISTOR AND CMOS PERIPHERAL CIRCUITRY | Dec 30, 1987 | Abandoned |
Array
(
[id] => 2604111
[patent_doc_number] => 04933904
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-12
[patent_title] => 'Dense EPROM having serially coupled floating gate transistors'
[patent_app_type] => 1
[patent_app_number] => 7/134585
[patent_app_country] => US
[patent_app_date] => 1987-12-14
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[pdf_file] => patents/04/933/04933904.pdf
[firstpage_image] =>[orig_patent_app_number] => 134585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/134585 | Dense EPROM having serially coupled floating gate transistors | Dec 13, 1987 | Issued |
Array
(
[id] => 2491268
[patent_doc_number] => 04823314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-04-18
[patent_title] => 'Integrated circuit dual port static memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/132416
[patent_app_country] => US
[patent_app_date] => 1987-12-14
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[firstpage_image] =>[orig_patent_app_number] => 132416
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/132416 | Integrated circuit dual port static memory cell | Dec 13, 1987 | Issued |
| 07/131633 | BIT LINE STRUCTURE FOR SEMICONDUCTOR MEMORY DEVICE | Dec 10, 1987 | Abandoned |
Array
(
[id] => 2607128
[patent_doc_number] => 04924437
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-08
[patent_title] => 'Erasable programmable memory including buried diffusion source/drain lines and erase lines'
[patent_app_type] => 1
[patent_app_number] => 7/130774
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[patent_app_date] => 1987-12-09
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[firstpage_image] =>[orig_patent_app_number] => 130774
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/130774 | Erasable programmable memory including buried diffusion source/drain lines and erase lines | Dec 8, 1987 | Issued |
Array
(
[id] => 2643538
[patent_doc_number] => 04893282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-09
[patent_title] => 'Semiconductor memory device'
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[patent_app_number] => 7/133153
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[patent_app_date] => 1987-12-07
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[firstpage_image] =>[orig_patent_app_number] => 133153
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/133153 | Semiconductor memory device | Dec 6, 1987 | Issued |
Array
(
[id] => 2493007
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[patent_issue_date] => 1989-01-24
[patent_title] => 'Non-volatile memory having charge correction circuitry'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/129930 | Non-volatile memory having charge correction circuitry | Dec 2, 1987 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/126523 | Trench DRAM cell with dynamic gain | Nov 29, 1987 | Issued |
Array
(
[id] => 2525099
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[patent_issue_date] => 1989-10-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/127621 | Semiconductor memory with an improved nibble mode arrangement | Nov 29, 1987 | Issued |
Array
(
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