Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2501970 [patent_doc_number] => 04843596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-27 [patent_title] => 'Semiconductor memory device with address transition detection and timing control' [patent_app_type] => 1 [patent_app_number] => 7/124554 [patent_app_country] => US [patent_app_date] => 1987-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2343 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/843/04843596.pdf [firstpage_image] =>[orig_patent_app_number] => 124554 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/124554
Semiconductor memory device with address transition detection and timing control Nov 23, 1987 Issued
07/120227 DOUBLE SIDED OPTICAL MEMORY ELEMENT Nov 9, 1987 Abandoned
Array ( [id] => 2572640 [patent_doc_number] => 04849935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'Semiconductor memory including transparent latch circuits' [patent_app_type] => 1 [patent_app_number] => 7/113204 [patent_app_country] => US [patent_app_date] => 1987-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2824 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849935.pdf [firstpage_image] =>[orig_patent_app_number] => 113204 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/113204
Semiconductor memory including transparent latch circuits Oct 26, 1987 Issued
Array ( [id] => 2655264 [patent_doc_number] => 04896297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-23 [patent_title] => 'Circuit for generating a boosted signal for a word line' [patent_app_type] => 1 [patent_app_number] => 7/112034 [patent_app_country] => US [patent_app_date] => 1987-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3703 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/896/04896297.pdf [firstpage_image] =>[orig_patent_app_number] => 112034 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/112034
Circuit for generating a boosted signal for a word line Oct 22, 1987 Issued
Array ( [id] => 2499152 [patent_doc_number] => 04829481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-09 [patent_title] => 'Defective element disabling circuit having a laser-blown fuse' [patent_app_type] => 1 [patent_app_number] => 7/112255 [patent_app_country] => US [patent_app_date] => 1987-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2011 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/829/04829481.pdf [firstpage_image] =>[orig_patent_app_number] => 112255 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/112255
Defective element disabling circuit having a laser-blown fuse Oct 21, 1987 Issued
Array ( [id] => 2643759 [patent_doc_number] => 04953127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Semiconductor memory having different read and write word line voltage levels' [patent_app_type] => 1 [patent_app_number] => 7/110823 [patent_app_country] => US [patent_app_date] => 1987-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6752 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/953/04953127.pdf [firstpage_image] =>[orig_patent_app_number] => 110823 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/110823
Semiconductor memory having different read and write word line voltage levels Oct 20, 1987 Issued
Array ( [id] => 2500931 [patent_doc_number] => 04860258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Electrically programmable non-volatile memory having sequentially deactivated write circuits' [patent_app_type] => 1 [patent_app_number] => 7/110274 [patent_app_country] => US [patent_app_date] => 1987-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4058 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/860/04860258.pdf [firstpage_image] =>[orig_patent_app_number] => 110274 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/110274
Electrically programmable non-volatile memory having sequentially deactivated write circuits Oct 19, 1987 Issued
Array ( [id] => 2499111 [patent_doc_number] => 04829479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-09 [patent_title] => 'Memory device with improved common data line bias arrangement' [patent_app_type] => 1 [patent_app_number] => 7/108623 [patent_app_country] => US [patent_app_date] => 1987-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/829/04829479.pdf [firstpage_image] =>[orig_patent_app_number] => 108623 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/108623
Memory device with improved common data line bias arrangement Oct 14, 1987 Issued
Array ( [id] => 2532944 [patent_doc_number] => 04873666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Message FIFO buffer controller' [patent_app_type] => 1 [patent_app_number] => 7/108655 [patent_app_country] => US [patent_app_date] => 1987-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5860 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873666.pdf [firstpage_image] =>[orig_patent_app_number] => 108655 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/108655
Message FIFO buffer controller Oct 14, 1987 Issued
Array ( [id] => 2532962 [patent_doc_number] => 04873667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'FIFO buffer controller' [patent_app_type] => 1 [patent_app_number] => 7/108653 [patent_app_country] => US [patent_app_date] => 1987-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5714 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873667.pdf [firstpage_image] =>[orig_patent_app_number] => 108653 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/108653
FIFO buffer controller Oct 14, 1987 Issued
Array ( [id] => 2692028 [patent_doc_number] => 05046043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Ferroelectric capacitor and memory cell including barrier and isolation layers' [patent_app_type] => 1 [patent_app_number] => 7/105578 [patent_app_country] => US [patent_app_date] => 1987-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4925 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/046/05046043.pdf [firstpage_image] =>[orig_patent_app_number] => 105578 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/105578
Ferroelectric capacitor and memory cell including barrier and isolation layers Oct 7, 1987 Issued
Array ( [id] => 2595365 [patent_doc_number] => 04908793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-13 [patent_title] => 'Storage apparatus including a semiconductor memory and a disk drive' [patent_app_type] => 1 [patent_app_number] => 7/105844 [patent_app_country] => US [patent_app_date] => 1987-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1790 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/908/04908793.pdf [firstpage_image] =>[orig_patent_app_number] => 105844 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/105844
Storage apparatus including a semiconductor memory and a disk drive Oct 7, 1987 Issued
07/102993 HIGH SPEED EPROM INCLUDING MEMORY CELLS HAVING ELONGATED CONTROL GATES Sep 29, 1987 Abandoned
Array ( [id] => 2491410 [patent_doc_number] => 04823322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Dynamic random access memory device having an improved timing arrangement' [patent_app_type] => 1 [patent_app_number] => 7/102683 [patent_app_country] => US [patent_app_date] => 1987-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3116 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823322.pdf [firstpage_image] =>[orig_patent_app_number] => 102683 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/102683
Dynamic random access memory device having an improved timing arrangement Sep 29, 1987 Issued
Array ( [id] => 2606842 [patent_doc_number] => 04965770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-23 [patent_title] => 'Semiconductor memory capable of simultaneously reading plural adjacent memory cells' [patent_app_type] => 1 [patent_app_number] => 7/101380 [patent_app_country] => US [patent_app_date] => 1987-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10028 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/965/04965770.pdf [firstpage_image] =>[orig_patent_app_number] => 101380 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/101380
Semiconductor memory capable of simultaneously reading plural adjacent memory cells Sep 24, 1987 Issued
07/101367 OPTICAL INFORMATION METHOD FOR RECORDING AND ERASING INFORMATION Sep 24, 1987 Abandoned
Array ( [id] => 2457998 [patent_doc_number] => 04768166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-30 [patent_title] => 'Semiconductor static memory device with cell grounding means for reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 7/097330 [patent_app_country] => US [patent_app_date] => 1987-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1962 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/768/04768166.pdf [firstpage_image] =>[orig_patent_app_number] => 097330 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/097330
Semiconductor static memory device with cell grounding means for reduced power consumption Sep 9, 1987 Issued
Array ( [id] => 2487238 [patent_doc_number] => 04882710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-21 [patent_title] => 'FIFO memory including dynamic memory elements' [patent_app_type] => 1 [patent_app_number] => 7/094943 [patent_app_country] => US [patent_app_date] => 1987-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4384 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/882/04882710.pdf [firstpage_image] =>[orig_patent_app_number] => 094943 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/094943
FIFO memory including dynamic memory elements Sep 8, 1987 Issued
07/095053 NON-VOLATILE MEMORY DEVICE INCLUDING A MICRO-MECHANICAL STORAGE ELEMENT Sep 8, 1987 Abandoned
Array ( [id] => 2574449 [patent_doc_number] => 04858188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'Semiconductor memory with improved write function' [patent_app_type] => 1 [patent_app_number] => 7/093833 [patent_app_country] => US [patent_app_date] => 1987-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 3332 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/858/04858188.pdf [firstpage_image] =>[orig_patent_app_number] => 093833 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/093833
Semiconductor memory with improved write function Sep 7, 1987 Issued
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