Search

Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
07/088334 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MULTIDIRECTION DATA ACCESS Aug 20, 1987 Abandoned
Array ( [id] => 2529974 [patent_doc_number] => 04885719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-05 [patent_title] => 'Improved logic cell array using CMOS E.sup.2 PROM cells' [patent_app_type] => 1 [patent_app_number] => 7/087143 [patent_app_country] => US [patent_app_date] => 1987-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1856 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/885/04885719.pdf [firstpage_image] =>[orig_patent_app_number] => 087143 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/087143
Improved logic cell array using CMOS E.sup.2 PROM cells Aug 18, 1987 Issued
Array ( [id] => 2498922 [patent_doc_number] => 04868789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Random access memory system with circuitry for avoiding use of defective memory cells' [patent_app_type] => 1 [patent_app_number] => 7/098623 [patent_app_country] => US [patent_app_date] => 1987-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8729 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868789.pdf [firstpage_image] =>[orig_patent_app_number] => 098623 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/098623
Random access memory system with circuitry for avoiding use of defective memory cells Aug 11, 1987 Issued
Array ( [id] => 2492940 [patent_doc_number] => 04800525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-24 [patent_title] => 'Dual ended folded bit line arrangement and addressing scheme' [patent_app_type] => 1 [patent_app_number] => 7/083911 [patent_app_country] => US [patent_app_date] => 1987-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4169 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/800/04800525.pdf [firstpage_image] =>[orig_patent_app_number] => 083911 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/083911
Dual ended folded bit line arrangement and addressing scheme Aug 5, 1987 Issued
Array ( [id] => 2455971 [patent_doc_number] => 04791608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-13 [patent_title] => 'Memory card having shutter protected terminals' [patent_app_type] => 1 [patent_app_number] => 7/080233 [patent_app_country] => US [patent_app_date] => 1987-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1187 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/791/04791608.pdf [firstpage_image] =>[orig_patent_app_number] => 080233 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/080233
Memory card having shutter protected terminals Jul 27, 1987 Issued
07/076223 MOS MEMORY DEVICE Jul 21, 1987 Abandoned
Array ( [id] => 2607110 [patent_doc_number] => 04924436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Data storage device having a phase change memory medium reversible by direct overwrite and method of direct overwrite' [patent_app_type] => 1 [patent_app_number] => 7/075502 [patent_app_country] => US [patent_app_date] => 1987-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3655 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/924/04924436.pdf [firstpage_image] =>[orig_patent_app_number] => 075502 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/075502
Data storage device having a phase change memory medium reversible by direct overwrite and method of direct overwrite Jul 19, 1987 Issued
Array ( [id] => 2830662 [patent_doc_number] => 05173872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-22 [patent_title] => 'Content addressable memory for microprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/073054 [patent_app_country] => US [patent_app_date] => 1987-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4925 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/173/05173872.pdf [firstpage_image] =>[orig_patent_app_number] => 073054 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/073054
Content addressable memory for microprocessor system Jul 12, 1987 Issued
Array ( [id] => 2528533 [patent_doc_number] => 04855959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-08 [patent_title] => 'Dual port memory circuit' [patent_app_type] => 1 [patent_app_number] => 7/069744 [patent_app_country] => US [patent_app_date] => 1987-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3237 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 421 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/855/04855959.pdf [firstpage_image] =>[orig_patent_app_number] => 069744 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/069744
Dual port memory circuit Jul 5, 1987 Issued
Array ( [id] => 2486672 [patent_doc_number] => 04876667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-24 [patent_title] => 'Data storage device having a phase change memory medium reversible by direct overwrite' [patent_app_type] => 1 [patent_app_number] => 7/064645 [patent_app_country] => US [patent_app_date] => 1987-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2468 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/876/04876667.pdf [firstpage_image] =>[orig_patent_app_number] => 064645 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/064645
Data storage device having a phase change memory medium reversible by direct overwrite Jun 21, 1987 Issued
Array ( [id] => 2643461 [patent_doc_number] => 04893278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-09 [patent_title] => 'Semiconductor memory device including precharge/equalization circuitry for the complementary data lines' [patent_app_type] => 1 [patent_app_number] => 7/060334 [patent_app_country] => US [patent_app_date] => 1987-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9174 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/893/04893278.pdf [firstpage_image] =>[orig_patent_app_number] => 060334 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/060334
Semiconductor memory device including precharge/equalization circuitry for the complementary data lines Jun 9, 1987 Issued
Array ( [id] => 2572600 [patent_doc_number] => 04849933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'Bipolar programmable logic array' [patent_app_type] => 1 [patent_app_number] => 7/047794 [patent_app_country] => US [patent_app_date] => 1987-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4214 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849933.pdf [firstpage_image] =>[orig_patent_app_number] => 047794 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/047794
Bipolar programmable logic array May 5, 1987 Issued
Array ( [id] => 2565243 [patent_doc_number] => 04809234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-28 [patent_title] => 'Memory device including memories having different capacities' [patent_app_type] => 1 [patent_app_number] => 7/046424 [patent_app_country] => US [patent_app_date] => 1987-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2395 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/809/04809234.pdf [firstpage_image] =>[orig_patent_app_number] => 046424 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/046424
Memory device including memories having different capacities May 5, 1987 Issued
Array ( [id] => 2520297 [patent_doc_number] => 04831596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'Pass gate with low transistor junction breakdown susceptibility' [patent_app_type] => 1 [patent_app_number] => 7/045914 [patent_app_country] => US [patent_app_date] => 1987-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2735 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/831/04831596.pdf [firstpage_image] =>[orig_patent_app_number] => 045914 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/045914
Pass gate with low transistor junction breakdown susceptibility Apr 30, 1987 Issued
Array ( [id] => 2562886 [patent_doc_number] => 04803657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-07 [patent_title] => 'Serial first-in-first-out (FIFO) memory and method for clocking the same' [patent_app_type] => 1 [patent_app_number] => 7/043384 [patent_app_country] => US [patent_app_date] => 1987-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4617 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 625 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/803/04803657.pdf [firstpage_image] =>[orig_patent_app_number] => 043384 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/043384
Serial first-in-first-out (FIFO) memory and method for clocking the same Apr 27, 1987 Issued
Array ( [id] => 2504076 [patent_doc_number] => 04847808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-11 [patent_title] => 'Read only semiconductor memory having multiple bit cells' [patent_app_type] => 1 [patent_app_number] => 7/041033 [patent_app_country] => US [patent_app_date] => 1987-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3815 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/847/04847808.pdf [firstpage_image] =>[orig_patent_app_number] => 041033 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/041033
Read only semiconductor memory having multiple bit cells Apr 21, 1987 Issued
07/040753 STATIC SEMICONDUCTOR MEMORY WITH READOUT INHIBIT MEANS Apr 14, 1987 Abandoned
07/048074 SELF-IDENTIFYING SCHEME FOR MEMORY Apr 10, 1987 Abandoned
Array ( [id] => 2567771 [patent_doc_number] => 04817052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit' [patent_app_type] => 1 [patent_app_number] => 7/037048 [patent_app_country] => US [patent_app_date] => 1987-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 13305 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/817/04817052.pdf [firstpage_image] =>[orig_patent_app_number] => 037048 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/037048
Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit Apr 9, 1987 Issued
Array ( [id] => 2561796 [patent_doc_number] => 04833650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-23 [patent_title] => 'Semiconductor memory device including programmable mode selection circuitry' [patent_app_type] => 1 [patent_app_number] => 7/034094 [patent_app_country] => US [patent_app_date] => 1987-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2399 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/833/04833650.pdf [firstpage_image] =>[orig_patent_app_number] => 034094 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/034094
Semiconductor memory device including programmable mode selection circuitry Apr 1, 1987 Issued
Menu