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Danielle Jackson

Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
1037
Issued Applications
648
Pending Applications
53
Abandoned Applications
355

Applications

Application numberTitle of the applicationFiling DateStatus
07/029763 NON-VOLATILE MEMORY HAVING IMPROVED TESTING CIRCUITRY Mar 23, 1987 Abandoned
07/021561 SEMICONDUCTOR MEMORY DEVICE HAVING AT LEAST ONE NON-VOLATILE MEMORY TRANSISTOR Mar 1, 1987 Abandoned
Array ( [id] => 2502117 [patent_doc_number] => 04825413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-25 [patent_title] => 'Bipolar-CMOS static ram memory device' [patent_app_type] => 1 [patent_app_number] => 7/018874 [patent_app_country] => US [patent_app_date] => 1987-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2492 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/825/04825413.pdf [firstpage_image] =>[orig_patent_app_number] => 018874 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/018874
Bipolar-CMOS static ram memory device Feb 23, 1987 Issued
07/013204 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH AN IMPROVED COUPLING ARRANGEMENT FOR LOGIC UNITS OR LOGIC BLOCKS Feb 5, 1987 Abandoned
Array ( [id] => 2574487 [patent_doc_number] => 04858190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'Dual port semiconductor memory having random and serial access modes' [patent_app_type] => 1 [patent_app_number] => 7/005104 [patent_app_country] => US [patent_app_date] => 1987-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8675 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/858/04858190.pdf [firstpage_image] =>[orig_patent_app_number] => 005104 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/005104
Dual port semiconductor memory having random and serial access modes Jan 19, 1987 Issued
Array ( [id] => 2520181 [patent_doc_number] => 04831590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'Semiconductor memory including an output latch having hysteresis characteristics' [patent_app_type] => 1 [patent_app_number] => 7/004584 [patent_app_country] => US [patent_app_date] => 1987-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5521 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/831/04831590.pdf [firstpage_image] =>[orig_patent_app_number] => 004584 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/004584
Semiconductor memory including an output latch having hysteresis characteristics Jan 19, 1987 Issued
Array ( [id] => 2568063 [patent_doc_number] => 04853892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-01 [patent_title] => 'Associative memory device including write inhibit circuitry' [patent_app_type] => 1 [patent_app_number] => 7/004004 [patent_app_country] => US [patent_app_date] => 1987-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3720 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/853/04853892.pdf [firstpage_image] =>[orig_patent_app_number] => 004004 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/004004
Associative memory device including write inhibit circuitry Jan 15, 1987 Issued
Array ( [id] => 2757001 [patent_doc_number] => 05016214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Memory cell with separate read and write paths and clamping transistors' [patent_app_type] => 1 [patent_app_number] => 7/003114 [patent_app_country] => US [patent_app_date] => 1987-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2745 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/016/05016214.pdf [firstpage_image] =>[orig_patent_app_number] => 003114 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/003114
Memory cell with separate read and write paths and clamping transistors Jan 13, 1987 Issued
Array ( [id] => 2484279 [patent_doc_number] => 04872139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-03 [patent_title] => 'Memory protection device for an electronic apparatus' [patent_app_type] => 1 [patent_app_number] => 7/002194 [patent_app_country] => US [patent_app_date] => 1987-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1078 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/872/04872139.pdf [firstpage_image] =>[orig_patent_app_number] => 002194 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/002194
Memory protection device for an electronic apparatus Jan 11, 1987 Issued
Array ( [id] => 2824120 [patent_doc_number] => 05122984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Parallel associative memory system' [patent_app_type] => 1 [patent_app_number] => 7/001233 [patent_app_country] => US [patent_app_date] => 1987-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 15878 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122984.pdf [firstpage_image] =>[orig_patent_app_number] => 001233 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/001233
Parallel associative memory system Jan 6, 1987 Issued
07/000463 SEMICONDUCTOR MEMORY Jan 4, 1987 Abandoned
Array ( [id] => 2451431 [patent_doc_number] => 04779230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-18 [patent_title] => 'CMOS static ram cell provided with an additional bipolar drive transistor' [patent_app_type] => 1 [patent_app_number] => 6/947124 [patent_app_country] => US [patent_app_date] => 1986-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1748 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/779/04779230.pdf [firstpage_image] =>[orig_patent_app_number] => 947124 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/947124
CMOS static ram cell provided with an additional bipolar drive transistor Dec 28, 1986 Issued
Array ( [id] => 2486018 [patent_doc_number] => 04813016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-14 [patent_title] => 'Tunnel memory device having a multi-layered Langmuir-Blodgett film' [patent_app_type] => 1 [patent_app_number] => 6/947504 [patent_app_country] => US [patent_app_date] => 1986-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4044 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/813/04813016.pdf [firstpage_image] =>[orig_patent_app_number] => 947504 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/947504
Tunnel memory device having a multi-layered Langmuir-Blodgett film Dec 28, 1986 Issued
Array ( [id] => 2493065 [patent_doc_number] => 04800531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-24 [patent_title] => 'Address buffer circuit for a dram' [patent_app_type] => 1 [patent_app_number] => 6/944784 [patent_app_country] => US [patent_app_date] => 1986-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4896 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/800/04800531.pdf [firstpage_image] =>[orig_patent_app_number] => 944784 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/944784
Address buffer circuit for a dram Dec 21, 1986 Issued
Array ( [id] => 2644616 [patent_doc_number] => 04899308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-06 [patent_title] => 'High density ROM in a CMOS gate array' [patent_app_type] => 1 [patent_app_number] => 6/940363 [patent_app_country] => US [patent_app_date] => 1986-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4164 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/899/04899308.pdf [firstpage_image] =>[orig_patent_app_number] => 940363 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/940363
High density ROM in a CMOS gate array Dec 10, 1986 Issued
Array ( [id] => 2555723 [patent_doc_number] => 04805141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-14 [patent_title] => 'Bipolar PROM having transistors with reduced base widths' [patent_app_type] => 1 [patent_app_number] => 6/929433 [patent_app_country] => US [patent_app_date] => 1986-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4242 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/805/04805141.pdf [firstpage_image] =>[orig_patent_app_number] => 929433 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/929433
Bipolar PROM having transistors with reduced base widths Nov 11, 1986 Issued
Array ( [id] => 2491250 [patent_doc_number] => 04823313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Memory device with comparison function' [patent_app_type] => 1 [patent_app_number] => 6/930364 [patent_app_country] => US [patent_app_date] => 1986-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3641 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823313.pdf [firstpage_image] =>[orig_patent_app_number] => 930364 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/930364
Memory device with comparison function Nov 11, 1986 Issued
06/929345 SEMICONDUCTOR MEMORY HAVING AMPLIFIER INCLUDING BIPOLAR TRANSISTOR Nov 11, 1986 Abandoned
Array ( [id] => 2517896 [patent_doc_number] => 04796234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-03 [patent_title] => 'Semiconductor memory having selectively activated blocks including CMOS sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 6/927144 [patent_app_country] => US [patent_app_date] => 1986-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6743 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/796/04796234.pdf [firstpage_image] =>[orig_patent_app_number] => 927144 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/927144
Semiconductor memory having selectively activated blocks including CMOS sense amplifiers Nov 4, 1986 Issued
Array ( [id] => 2598647 [patent_doc_number] => 04959811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-25 [patent_title] => 'Content addressable memory including comparison inhibit and shift register circuits' [patent_app_type] => 1 [patent_app_number] => 6/926433 [patent_app_country] => US [patent_app_date] => 1986-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7335 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/959/04959811.pdf [firstpage_image] =>[orig_patent_app_number] => 926433 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/926433
Content addressable memory including comparison inhibit and shift register circuits Nov 2, 1986 Issued
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