Danielle Jackson

Array ( [id] => 2397736 [patent_doc_number] => 04794567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-27 [patent_title] => 'Static memory including data buffer and latch circuits' [patent_app_type] => 1 [patent_app_number] => 6/924388 [patent_app_country] => US [patent_app_date] => 1986-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3213 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/794/04794567.pdf [firstpage_image] =>[orig_patent_app_number] => 924388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2558120 [patent_doc_number] => 04811287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-07 [patent_title] => 'EEPROM mounting device' [patent_app_type] => 1 [patent_app_number] => 6/923783 [patent_app_country] => US [patent_app_date] => 1986-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2635 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/811/04811287.pdf [firstpage_image] =>[orig_patent_app_number] => 923783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2561930 [patent_doc_number] => 04833657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-23 [patent_title] => 'Semiconductor frame buffer memory' [patent_app_type] => 1 [patent_app_number] => 6/923044 [patent_app_country] => US [patent_app_date] => 1986-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3957 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/833/04833657.pdf [firstpage_image] =>[orig_patent_app_number] => 923044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2461750 [patent_doc_number] => 04766568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-23 [patent_title] => 'Generic associative memory' [patent_app_type] => 1 [patent_app_number] => 6/915920 [patent_app_country] => US [patent_app_date] => 1986-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6053 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/766/04766568.pdf [firstpage_image] =>[orig_patent_app_number] => 915920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2555875 [patent_doc_number] => 04805149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-14 [patent_title] => 'Digital memory with reset/preset capabilities' [patent_app_type] => 1 [patent_app_number] => 6/901914 [patent_app_country] => US [patent_app_date] => 1986-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3108 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/805/04805149.pdf [firstpage_image] =>[orig_patent_app_number] => 901914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2511049 [patent_doc_number] => 04799192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-17 [patent_title] => 'Three-transistor content addressable memory' [patent_app_type] => 1 [patent_app_number] => 6/901514 [patent_app_country] => US [patent_app_date] => 1986-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3075 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/799/04799192.pdf [firstpage_image] =>[orig_patent_app_number] => 901514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2401798 [patent_doc_number] => 04769784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-06 [patent_title] => 'Capacitor-plate bias generator for CMOS DRAM memories' [patent_app_type] => 1 [patent_app_number] => 6/897893 [patent_app_country] => US [patent_app_date] => 1986-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3840 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/769/04769784.pdf [firstpage_image] =>[orig_patent_app_number] => 897893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2429868 [patent_doc_number] => 04788667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-29 [patent_title] => 'Semiconductor memory device having nibble mode function' [patent_app_type] => 1 [patent_app_number] => 6/895113 [patent_app_country] => US [patent_app_date] => 1986-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5127 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/788/04788667.pdf [firstpage_image] =>[orig_patent_app_number] => 895113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2552453 [patent_doc_number] => 04827452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-02 [patent_title] => 'Semiconductor memory including a selectively disabled redunancy circuit' [patent_app_type] => 1 [patent_app_number] => 6/894023 [patent_app_country] => US [patent_app_date] => 1986-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4039 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/827/04827452.pdf [firstpage_image] =>[orig_patent_app_number] => 894023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2401936 [patent_doc_number] => 04769791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-06 [patent_title] => 'On-chip pulse-width control circuit for SRAM memories' [patent_app_type] => 1 [patent_app_number] => 6/894584 [patent_app_country] => US [patent_app_date] => 1986-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2626 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 572 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/769/04769791.pdf [firstpage_image] =>[orig_patent_app_number] => 894584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2561816 [patent_doc_number] => 04833651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-23 [patent_title] => 'High-speed, asynchronous, No-Fall-Through, first-in-first out memory with high data integrity' [patent_app_type] => 1 [patent_app_number] => 6/889824 [patent_app_country] => US [patent_app_date] => 1986-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 59 [patent_no_of_words] => 7327 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/833/04833651.pdf [firstpage_image] =>[orig_patent_app_number] => 889824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2504095 [patent_doc_number] => 04847809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-11 [patent_title] => 'Image memory having standard dynamic RAM chips' [patent_app_type] => 1 [patent_app_number] => 6/883733 [patent_app_country] => US [patent_app_date] => 1986-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 9216 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/847/04847809.pdf [firstpage_image] =>[orig_patent_app_number] => 883733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2422111 [patent_doc_number] => 04787067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-22 [patent_title] => 'Semiconductor dynamic memory device having improved refreshing' [patent_app_type] => 1 [patent_app_number] => 6/883804 [patent_app_country] => US [patent_app_date] => 1986-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4167 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/787/04787067.pdf [firstpage_image] =>[orig_patent_app_number] => 883804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2422249 [patent_doc_number] => 04742488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-03 [patent_title] => 'Sense amplifier/write circuit for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 6/883357 [patent_app_country] => US [patent_app_date] => 1986-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3414 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/742/04742488.pdf [firstpage_image] =>[orig_patent_app_number] => 883357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2432770 [patent_doc_number] => 04763304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-09 [patent_title] => 'Semiconductor random access memory device having switchable input and output bit forms' [patent_app_type] => 1 [patent_app_number] => 6/882534 [patent_app_country] => US [patent_app_date] => 1986-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3867 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/763/04763304.pdf [firstpage_image] =>[orig_patent_app_number] => 882534 [rel_patent_id] =>[rel_patent_doc_number] =>)