| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[id] => 2421919
[patent_doc_number] => 04719598
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-01-12
[patent_title] => 'Bit addressable programming arrangement'
[patent_app_type] => 1
[patent_app_number] => 6/739843
[patent_app_country] => US
[patent_app_date] => 1985-05-31
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[firstpage_image] =>[orig_patent_app_number] => 739843
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/739843 | Bit addressable programming arrangement | May 30, 1985 | Issued |
Array
(
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[patent_doc_number] => 04679172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-07-07
[patent_title] => 'Dynamic memory with increased data retention time'
[patent_app_type] => 1
[patent_app_number] => 6/738664
[patent_app_country] => US
[patent_app_date] => 1985-05-28
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[pdf_file] => patents/04/679/04679172.pdf
[firstpage_image] =>[orig_patent_app_number] => 738664
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/738664 | Dynamic memory with increased data retention time | May 27, 1985 | Issued |
Array
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[patent_doc_number] => 04672579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-09
[patent_title] => 'MTL storage cell with inherent output multiplex capability'
[patent_app_type] => 1
[patent_app_number] => 6/737604
[patent_app_country] => US
[patent_app_date] => 1985-05-24
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[pdf_file] => patents/04/672/04672579.pdf
[firstpage_image] =>[orig_patent_app_number] => 737604
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/737604 | MTL storage cell with inherent output multiplex capability | May 23, 1985 | Issued |
Array
(
[id] => 2486110
[patent_doc_number] => 04813021
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-03-14
[patent_title] => 'Semiconductor memory device with delayed precharge signals'
[patent_app_type] => 1
[patent_app_number] => 6/735724
[patent_app_country] => US
[patent_app_date] => 1985-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/04/813/04813021.pdf
[firstpage_image] =>[orig_patent_app_number] => 735724
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/735724 | Semiconductor memory device with delayed precharge signals | May 19, 1985 | Issued |
Array
(
[id] => 2455957
[patent_doc_number] => 04755971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-07-05
[patent_title] => 'Buffer memory for an input line of a digital interface'
[patent_app_type] => 1
[patent_app_number] => 6/728729
[patent_app_country] => US
[patent_app_date] => 1985-04-30
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[pdf_file] => patents/04/755/04755971.pdf
[firstpage_image] =>[orig_patent_app_number] => 728729
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/728729 | Buffer memory for an input line of a digital interface | Apr 29, 1985 | Issued |
Array
(
[id] => 2335309
[patent_doc_number] => 04672580
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-09
[patent_title] => 'Memory cell providing simultaneous non-destructive access to volatile and non-volatile data'
[patent_app_type] => 1
[patent_app_number] => 6/728963
[patent_app_country] => US
[patent_app_date] => 1985-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/672/04672580.pdf
[firstpage_image] =>[orig_patent_app_number] => 728963
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/728963 | Memory cell providing simultaneous non-destructive access to volatile and non-volatile data | Apr 29, 1985 | Issued |
| 06/728539 | SEMICONDUCTOR STATIC MEMORY DEVICE WITH CELL GROUNDING MEANS FOR REDUCED POWER CONSUMPTION | Apr 28, 1985 | Abandoned |
Array
(
[id] => 2393044
[patent_doc_number] => 04707808
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-11-17
[patent_title] => 'Small size, high speed GaAs data latch'
[patent_app_type] => 1
[patent_app_number] => 6/727958
[patent_app_country] => US
[patent_app_date] => 1985-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/04/707/04707808.pdf
[firstpage_image] =>[orig_patent_app_number] => 727958
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/727958 | Small size, high speed GaAs data latch | Apr 25, 1985 | Issued |
| 06/727414 | DOUBLE SIDED OPTICAL MEMORY ELEMENT | Apr 24, 1985 | Abandoned |
Array
(
[id] => 2364446
[patent_doc_number] => 04665507
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-05-12
[patent_title] => 'Semiconductor memory having load devices controlled by a write signal'
[patent_app_type] => 1
[patent_app_number] => 6/724765
[patent_app_country] => US
[patent_app_date] => 1985-04-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/665/04665507.pdf
[firstpage_image] =>[orig_patent_app_number] => 724765
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/724765 | Semiconductor memory having load devices controlled by a write signal | Apr 17, 1985 | Issued |
Array
(
[id] => 2309130
[patent_doc_number] => 04685088
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-08-04
[patent_title] => 'High performance memory system utilizing pipelining techniques'
[patent_app_type] => 1
[patent_app_number] => 6/722920
[patent_app_country] => US
[patent_app_date] => 1985-04-15
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[pdf_file] => patents/04/685/04685088.pdf
[firstpage_image] =>[orig_patent_app_number] => 722920
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/722920 | High performance memory system utilizing pipelining techniques | Apr 14, 1985 | Issued |
Array
(
[id] => 2300865
[patent_doc_number] => 04653029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-24
[patent_title] => 'MOS amplifier and semiconductor memory using the same'
[patent_app_type] => 1
[patent_app_number] => 6/720794
[patent_app_country] => US
[patent_app_date] => 1985-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/04/653/04653029.pdf
[firstpage_image] =>[orig_patent_app_number] => 720794
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/720794 | MOS amplifier and semiconductor memory using the same | Apr 7, 1985 | Issued |
| 06/719706 | DUPLICATOR IN A BUBBLE MEMORY WITH NON-IMPLANTED PATTERNS, PROCESS FOR PRODUCING SUCH A DUPLICATOR AND SERIAL-PARALLEL BUBBLE HAVING AT LEAST ONE OF THE SAID DUPLICATORS | Apr 3, 1985 | Abandoned |
Array
(
[id] => 2393137
[patent_doc_number] => 04754167
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-06-28
[patent_title] => 'Programmable reference voltage generator for a read only memory'
[patent_app_type] => 1
[patent_app_number] => 6/719928
[patent_app_country] => US
[patent_app_date] => 1985-04-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/754/04754167.pdf
[firstpage_image] =>[orig_patent_app_number] => 719928
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/719928 | Programmable reference voltage generator for a read only memory | Apr 3, 1985 | Issued |
Array
(
[id] => 2365044
[patent_doc_number] => 04694433
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-09-15
[patent_title] => 'Semiconductor memory having subarrays and partial word lines'
[patent_app_type] => 1
[patent_app_number] => 6/719945
[patent_app_country] => US
[patent_app_date] => 1985-04-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/719945 | Semiconductor memory having subarrays and partial word lines | Apr 3, 1985 | Issued |
Array
(
[id] => 2355604
[patent_doc_number] => 04692900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-09-08
[patent_title] => 'Semiconductor memory device having block pairs'
[patent_app_type] => 1
[patent_app_number] => 6/715835
[patent_app_country] => US
[patent_app_date] => 1985-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/04/692/04692900.pdf
[firstpage_image] =>[orig_patent_app_number] => 715835
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/715835 | Semiconductor memory device having block pairs | Mar 24, 1985 | Issued |
| 06/710295 | VIDEO DISPLAY MEMORY ARCHITECTURE | Mar 10, 1985 | Abandoned |
Array
(
[id] => 2561722
[patent_doc_number] => 04833646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-23
[patent_title] => 'Programmable logic device with limited sense currents and noise reduction'
[patent_app_type] => 1
[patent_app_number] => 6/707670
[patent_app_country] => US
[patent_app_date] => 1985-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 707670
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/707670 | Programmable logic device with limited sense currents and noise reduction | Mar 3, 1985 | Issued |
| 06/707354 | SEMICONDUCTOR MEMORY DEVICE HAVING AT LEAST ONE NON-VOLATILE MEMORY TRANSISTOR | Feb 28, 1985 | Abandoned |
Array
(
[id] => 2318022
[patent_doc_number] => 04646272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-24
[patent_title] => 'Data I/O circuit with higher integration density for DRAM'
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[patent_app_date] => 1985-03-01
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[firstpage_image] =>[orig_patent_app_number] => 706944
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/706944 | Data I/O circuit with higher integration density for DRAM | Feb 28, 1985 | Issued |