Danielle Jackson

Array ( [id] => 12248975 [patent_doc_number] => 09921749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Memory system and method including determining a read voltage based on program order information and a plurality of mapping tables' [patent_app_type] => utility [patent_app_number] => 14/743458 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 52 [patent_no_of_words] => 22962 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12101897 [patent_doc_number] => 09858994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Memory system with MLC memory cells and partial page compression or reduction' [patent_app_type] => utility [patent_app_number] => 14/743445 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 21388 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11770115 [patent_doc_number] => 09378799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands' [patent_app_type] => utility [patent_app_number] => 14/720524 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 10598 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14720524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10363325 [patent_doc_number] => 20150248330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'MEMORY SYSTEM PROVIDED WITH NAND FLASH MEMORY AND METHOD INCLUDING SIMULTANEOUSLY WRITING DATA TO FIRST AND SECOND DISTRICTS' [patent_app_type] => utility [patent_app_number] => 14/712687 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4439 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10357316 [patent_doc_number] => 20150242321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'METHOD AND SYSTEM FOR ENSURING RELIABILITY OF CACHE DATA AND METADATA SUBSEQUENT TO A REBOOT' [patent_app_type] => utility [patent_app_number] => 14/708525 [patent_app_country] => US [patent_app_date] => 2015-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14708525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12108044 [patent_doc_number] => 09864530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Method for writing data to virtual disk using a controller virtual machine and different storage and communication protocols on a single storage platform' [patent_app_type] => utility [patent_app_number] => 14/684086 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 18002 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10392762 [patent_doc_number] => 20150277769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SCALE-OUT STORAGE IN A VIRTUALIZED STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/669444 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10392761 [patent_doc_number] => 20150277768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'RELOCATING DATA BETWEEN STORAGE ARRAYS' [patent_app_type] => utility [patent_app_number] => 14/669437 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14614885 [patent_doc_number] => 10360144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Storage apparatus and non-volatile memory device including a controller to selectively compress data based on an update frequency level [patent_app_type] => utility [patent_app_number] => 15/545094 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12224 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 425 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15545094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173900 [patent_doc_number] => 09892044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Methods to efficiently implement coarse granularity cache eviction' [patent_app_type] => utility [patent_app_number] => 14/609889 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 18101 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173901 [patent_doc_number] => 09892045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Methods to select segments of an evicted cache unit for reinsertion into the cache' [patent_app_type] => utility [patent_app_number] => 14/609902 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 18084 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12249187 [patent_doc_number] => 09921963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Method to decrease computation for cache eviction using deferred calculations' [patent_app_type] => utility [patent_app_number] => 14/609928 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 18075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11816885 [patent_doc_number] => 09720835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Methods to efficiently implement coarse granularity cache eviction based on segment deletion hints' [patent_app_type] => utility [patent_app_number] => 14/609839 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 18093 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11027297 [patent_doc_number] => 20160224252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'HYBRID MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/609904 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11028503 [patent_doc_number] => 20160225459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'APPARATUSES OPERABLE IN MULTIPLE POWER MODES AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/609922 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5612 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10242985 [patent_doc_number] => 20150127980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR SYNCHRONIZING DATA WRITTEN TO TAPE INCLUDING WRITING AN INDEX INTO A DATA PARTITION' [patent_app_type] => utility [patent_app_number] => 14/591457 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10763957 [patent_doc_number] => 20160110112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'DATA WRITING METHOD, MEMOEY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/564113 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10252 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10816048 [patent_doc_number] => 20160162210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'OPENSTACK SWIFT INTERFACE FOR TAPE LIBRARY (OSSITL)' [patent_app_type] => utility [patent_app_number] => 14/564255 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6339 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11452027 [patent_doc_number] => 09575669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Programmable solid state drive controller and method for scheduling commands utilizing a data structure' [patent_app_type] => utility [patent_app_number] => 14/564829 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564829 [rel_patent_id] =>[rel_patent_doc_number] =>)