
Danielle Jackson
Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )
| Most Active Art Unit | 3636 |
| Art Unit(s) | 3636 |
| Total Applications | 1037 |
| Issued Applications | 648 |
| Pending Applications | 53 |
| Abandoned Applications | 355 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2226285
[patent_doc_number] => 04592026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-27
[patent_title] => 'Memory device resistant to soft errors'
[patent_app_type] => 1
[patent_app_number] => 6/564683
[patent_app_country] => US
[patent_app_date] => 1983-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 4929
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/592/04592026.pdf
[firstpage_image] =>[orig_patent_app_number] => 564683
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/564683 | Memory device resistant to soft errors | Dec 22, 1983 | Issued |
Array
(
[id] => 2274400
[patent_doc_number] => 04630241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-16
[patent_title] => 'Method of programming for programmable circuit in redundancy circuit system'
[patent_app_type] => 1
[patent_app_number] => 6/563504
[patent_app_country] => US
[patent_app_date] => 1983-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 8817
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 366
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/630/04630241.pdf
[firstpage_image] =>[orig_patent_app_number] => 563504
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/563504 | Method of programming for programmable circuit in redundancy circuit system | Dec 19, 1983 | Issued |
Array
(
[id] => 2238282
[patent_doc_number] => 04601017
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-07-15
[patent_title] => 'Semiconductor memory device having active pull-up circuits'
[patent_app_type] => 1
[patent_app_number] => 6/561964
[patent_app_country] => US
[patent_app_date] => 1983-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 30
[patent_no_of_words] => 4081
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/601/04601017.pdf
[firstpage_image] =>[orig_patent_app_number] => 561964
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/561964 | Semiconductor memory device having active pull-up circuits | Dec 14, 1983 | Issued |
Array
(
[id] => 2287208
[patent_doc_number] => 04627032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-02
[patent_title] => 'Glitch lockout circuit for memory array'
[patent_app_type] => 1
[patent_app_number] => 6/554914
[patent_app_country] => US
[patent_app_date] => 1983-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3264
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/627/04627032.pdf
[firstpage_image] =>[orig_patent_app_number] => 554914
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/554914 | Glitch lockout circuit for memory array | Nov 24, 1983 | Issued |
Array
(
[id] => 2458054
[patent_doc_number] => 04768169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-08-30
[patent_title] => 'Fault-tolerant memory array'
[patent_app_type] => 1
[patent_app_number] => 6/546593
[patent_app_country] => US
[patent_app_date] => 1983-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3669
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/768/04768169.pdf
[firstpage_image] =>[orig_patent_app_number] => 546593
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/546593 | Fault-tolerant memory array | Oct 27, 1983 | Issued |
| 06/535054 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH AN IMPROVED COUPLING ARRANGEMENT FOR LOGIC UNITS OR LOGIC BLOCKS | Sep 22, 1983 | Abandoned |
| 06/534484 | STATIC RAM HAVING IMPROVED BIT LINE AND COLUMN CIRCUITRY | Sep 20, 1983 | Abandoned |
Array
(
[id] => 2227466
[patent_doc_number] => 04583205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-15
[patent_title] => 'Programmable memory circuit with an improved programming voltage applying circuit'
[patent_app_type] => 1
[patent_app_number] => 6/532923
[patent_app_country] => US
[patent_app_date] => 1983-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3426
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/583/04583205.pdf
[firstpage_image] =>[orig_patent_app_number] => 532923
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/532923 | Programmable memory circuit with an improved programming voltage applying circuit | Sep 15, 1983 | Issued |
Array
(
[id] => 2225025
[patent_doc_number] => 04596004
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-06-17
[patent_title] => 'High speed memory with a multiplexed address bus'
[patent_app_type] => 1
[patent_app_number] => 6/532113
[patent_app_country] => US
[patent_app_date] => 1983-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3386
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/596/04596004.pdf
[firstpage_image] =>[orig_patent_app_number] => 532113
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/532113 | High speed memory with a multiplexed address bus | Sep 13, 1983 | Issued |
Array
(
[id] => 2286724
[patent_doc_number] => 04623989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-11-18
[patent_title] => 'Memory with p-channel cell access transistors'
[patent_app_type] => 1
[patent_app_number] => 6/528204
[patent_app_country] => US
[patent_app_date] => 1983-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4201
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/623/04623989.pdf
[firstpage_image] =>[orig_patent_app_number] => 528204
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/528204 | Memory with p-channel cell access transistors | Aug 30, 1983 | Issued |
Array
(
[id] => 2309118
[patent_doc_number] => 04685087
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-08-04
[patent_title] => 'SRAM with constant pulse width'
[patent_app_type] => 1
[patent_app_number] => 6/528374
[patent_app_country] => US
[patent_app_date] => 1983-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3890
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/685/04685087.pdf
[firstpage_image] =>[orig_patent_app_number] => 528374
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/528374 | SRAM with constant pulse width | Aug 30, 1983 | Issued |
Array
(
[id] => 2226156
[patent_doc_number] => 04592019
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-27
[patent_title] => 'Bus oriented LIFO/FIFO memory'
[patent_app_type] => 1
[patent_app_number] => 6/527982
[patent_app_country] => US
[patent_app_date] => 1983-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 5940
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/592/04592019.pdf
[firstpage_image] =>[orig_patent_app_number] => 527982
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/527982 | Bus oriented LIFO/FIFO memory | Aug 30, 1983 | Issued |
Array
(
[id] => 2602624
[patent_doc_number] => 04918658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-17
[patent_title] => 'Static random access memory with asynchronous power-down'
[patent_app_type] => 1
[patent_app_number] => 6/528203
[patent_app_country] => US
[patent_app_date] => 1983-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2927
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/918/04918658.pdf
[firstpage_image] =>[orig_patent_app_number] => 528203
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/528203 | Static random access memory with asynchronous power-down | Aug 30, 1983 | Issued |
Array
(
[id] => 2233942
[patent_doc_number] => 04571705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-18
[patent_title] => 'Nonvolatile semiconductor memory device with electrically selectable, erasable and programmable function'
[patent_app_type] => 1
[patent_app_number] => 6/527483
[patent_app_country] => US
[patent_app_date] => 1983-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2692
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/571/04571705.pdf
[firstpage_image] =>[orig_patent_app_number] => 527483
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/527483 | Nonvolatile semiconductor memory device with electrically selectable, erasable and programmable function | Aug 28, 1983 | Issued |
Array
(
[id] => 2226141
[patent_doc_number] => 04592018
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-27
[patent_title] => 'Removable RAM package for ambulatory medical monitor'
[patent_app_type] => 1
[patent_app_number] => 6/527453
[patent_app_country] => US
[patent_app_date] => 1983-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1535
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/592/04592018.pdf
[firstpage_image] =>[orig_patent_app_number] => 527453
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/527453 | Removable RAM package for ambulatory medical monitor | Aug 28, 1983 | Issued |
Array
(
[id] => 2287125
[patent_doc_number] => 04627027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-02
[patent_title] => 'Analog storing and reproducing apparatus utilizing non-volatile memory elements'
[patent_app_type] => 1
[patent_app_number] => 6/525814
[patent_app_country] => US
[patent_app_date] => 1983-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 10783
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 660
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/627/04627027.pdf
[firstpage_image] =>[orig_patent_app_number] => 525814
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/525814 | Analog storing and reproducing apparatus utilizing non-volatile memory elements | Aug 22, 1983 | Issued |
Array
(
[id] => 2252083
[patent_doc_number] => 04633439
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-30
[patent_title] => 'Superconducting read-only memories or programable logic arrays having the same'
[patent_app_type] => 1
[patent_app_number] => 6/515514
[patent_app_country] => US
[patent_app_date] => 1983-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 31
[patent_no_of_words] => 4813
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/633/04633439.pdf
[firstpage_image] =>[orig_patent_app_number] => 515514
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/515514 | Superconducting read-only memories or programable logic arrays having the same | Jul 19, 1983 | Issued |
Array
(
[id] => 2142609
[patent_doc_number] => 04532606
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-30
[patent_title] => 'Content addressable memory cell with shift capability'
[patent_app_type] => 1
[patent_app_number] => 6/513393
[patent_app_country] => US
[patent_app_date] => 1983-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5210
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/532/04532606.pdf
[firstpage_image] =>[orig_patent_app_number] => 513393
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/513393 | Content addressable memory cell with shift capability | Jul 13, 1983 | Issued |
Array
(
[id] => 2275121
[patent_doc_number] => 04566080
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-01-21
[patent_title] => 'Byte wide EEPROM with individual write circuits'
[patent_app_type] => 1
[patent_app_number] => 6/512853
[patent_app_country] => US
[patent_app_date] => 1983-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4550
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/566/04566080.pdf
[firstpage_image] =>[orig_patent_app_number] => 512853
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/512853 | Byte wide EEPROM with individual write circuits | Jul 10, 1983 | Issued |
Array
(
[id] => 2218997
[patent_doc_number] => 04616341
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-10-07
[patent_title] => 'Directory memory system having simultaneous write and comparison data bypass capabilities'
[patent_app_type] => 1
[patent_app_number] => 6/509674
[patent_app_country] => US
[patent_app_date] => 1983-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2609
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/616/04616341.pdf
[firstpage_image] =>[orig_patent_app_number] => 509674
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/509674 | Directory memory system having simultaneous write and comparison data bypass capabilities | Jun 29, 1983 | Issued |