
Danielle Jackson
Examiner (ID: 13276, Phone: (571)272-2268 , Office: P/3636 )
| Most Active Art Unit | 3636 |
| Art Unit(s) | 3636 |
| Total Applications | 1037 |
| Issued Applications | 648 |
| Pending Applications | 53 |
| Abandoned Applications | 355 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2243162
[patent_doc_number] => 04586169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-29
[patent_title] => 'Semiconductor memory circuit and large scale integrated circuit using the same'
[patent_app_type] => 1
[patent_app_number] => 6/440723
[patent_app_country] => US
[patent_app_date] => 1982-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3595
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/586/04586169.pdf
[firstpage_image] =>[orig_patent_app_number] => 440723
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/440723 | Semiconductor memory circuit and large scale integrated circuit using the same | Nov 9, 1982 | Issued |
| 06/436743 | SENSE AMPLIFIER CIRCUIT FOR SEMICONDUCTOR MEMORIES | Oct 24, 1982 | Abandoned |
Array
(
[id] => 2281746
[patent_doc_number] => 04581721
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-04-08
[patent_title] => 'Memory apparatus with random and sequential addressing'
[patent_app_type] => 1
[patent_app_number] => 6/436484
[patent_app_country] => US
[patent_app_date] => 1982-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3348
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/581/04581721.pdf
[firstpage_image] =>[orig_patent_app_number] => 436484
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/436484 | Memory apparatus with random and sequential addressing | Oct 24, 1982 | Issued |
Array
(
[id] => 2218971
[patent_doc_number] => 04616340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-10-07
[patent_title] => 'Non-volatile semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 6/431304
[patent_app_country] => US
[patent_app_date] => 1982-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 3549
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 341
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/616/04616340.pdf
[firstpage_image] =>[orig_patent_app_number] => 431304
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/431304 | Non-volatile semiconductor memory | Sep 29, 1982 | Issued |
Array
(
[id] => 2204546
[patent_doc_number] => 04527258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-02
[patent_title] => 'E.sup.2 PROM having bulk storage'
[patent_app_type] => 1
[patent_app_number] => 6/431464
[patent_app_country] => US
[patent_app_date] => 1982-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3202
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/527/04527258.pdf
[firstpage_image] =>[orig_patent_app_number] => 431464
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/431464 | E.sup.2 PROM having bulk storage | Sep 29, 1982 | Issued |
Array
(
[id] => 2267054
[patent_doc_number] => 04570241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-11
[patent_title] => 'FET Storage with partitioned bit lines'
[patent_app_type] => 1
[patent_app_number] => 6/423983
[patent_app_country] => US
[patent_app_date] => 1982-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1906
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/570/04570241.pdf
[firstpage_image] =>[orig_patent_app_number] => 423983
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/423983 | FET Storage with partitioned bit lines | Sep 26, 1982 | Issued |
Array
(
[id] => 2147497
[patent_doc_number] => 04553225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-11-12
[patent_title] => 'Method of testing IC memories'
[patent_app_type] => 1
[patent_app_number] => 6/423645
[patent_app_country] => US
[patent_app_date] => 1982-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2530
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/553/04553225.pdf
[firstpage_image] =>[orig_patent_app_number] => 423645
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/423645 | Method of testing IC memories | Sep 26, 1982 | Issued |
Array
(
[id] => 2247733
[patent_doc_number] => 04567578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-01-28
[patent_title] => 'Cache memory flush scheme'
[patent_app_type] => 1
[patent_app_number] => 6/416034
[patent_app_country] => US
[patent_app_date] => 1982-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2540
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/567/04567578.pdf
[firstpage_image] =>[orig_patent_app_number] => 416034
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/416034 | Cache memory flush scheme | Sep 7, 1982 | Issued |
| 06/415903 | VOLTAGE-DEPENDENT OPTICAL DEVICE, IN PARTICULAR WITH THE FUNCTION OF A VOLTAGE MEMORY | Sep 7, 1982 | Abandoned |
Array
(
[id] => 2225802
[patent_doc_number] => 04578778
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-03-25
[patent_title] => 'Semiconductor memory with load controlling feedback means to reduce power consumption'
[patent_app_type] => 1
[patent_app_number] => 6/413752
[patent_app_country] => US
[patent_app_date] => 1982-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5467
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/578/04578778.pdf
[firstpage_image] =>[orig_patent_app_number] => 413752
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/413752 | Semiconductor memory with load controlling feedback means to reduce power consumption | Aug 31, 1982 | Issued |
Array
(
[id] => 2125381
[patent_doc_number] => 04481609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1984-11-06
[patent_title] => 'Semiconductor memory miniaturized by line groups and staggered cells'
[patent_app_type] => 1
[patent_app_number] => 6/409404
[patent_app_country] => US
[patent_app_date] => 1982-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4543
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/481/04481609.pdf
[firstpage_image] =>[orig_patent_app_number] => 409404
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/409404 | Semiconductor memory miniaturized by line groups and staggered cells | Aug 18, 1982 | Issued |
| 06/409613 | SEMICONDUCTOR DEVICE | Aug 18, 1982 | Abandoned |
Array
(
[id] => 2271217
[patent_doc_number] => 04575823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-03-11
[patent_title] => 'Electrically alterable non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 6/409002
[patent_app_country] => US
[patent_app_date] => 1982-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 12045
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/575/04575823.pdf
[firstpage_image] =>[orig_patent_app_number] => 409002
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/409002 | Electrically alterable non-volatile memory | Aug 16, 1982 | Issued |
Array
(
[id] => 2205085
[patent_doc_number] => 04542484
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-09-17
[patent_title] => 'Sense amplifier with high speed, stabilized read-out'
[patent_app_type] => 1
[patent_app_number] => 6/405462
[patent_app_country] => US
[patent_app_date] => 1982-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 5421
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/542/04542484.pdf
[firstpage_image] =>[orig_patent_app_number] => 405462
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/405462 | Sense amplifier with high speed, stabilized read-out | Aug 4, 1982 | Issued |
| 06/401692 | SEMICONDUCTOR MEMORY DEVICE | Jul 25, 1982 | Abandoned |
Array
(
[id] => 2206283
[patent_doc_number] => 04528648
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-09
[patent_title] => 'Memory management system'
[patent_app_type] => 1
[patent_app_number] => 6/400335
[patent_app_country] => US
[patent_app_date] => 1982-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1772
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/528/04528648.pdf
[firstpage_image] =>[orig_patent_app_number] => 400335
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/400335 | Memory management system | Jul 20, 1982 | Issued |
Array
(
[id] => 2142617
[patent_doc_number] => 04532607
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-30
[patent_title] => 'Programmable circuit including a latch to store a fuse\'s state'
[patent_app_type] => 1
[patent_app_number] => 6/398925
[patent_app_country] => US
[patent_app_date] => 1982-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 4008
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/532/04532607.pdf
[firstpage_image] =>[orig_patent_app_number] => 398925
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/398925 | Programmable circuit including a latch to store a fuse's state | Jul 15, 1982 | Issued |
Array
(
[id] => 2206250
[patent_doc_number] => 04528646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-09
[patent_title] => 'Semiconductor memory with selectively enabled precharge and sense amplifier circuits'
[patent_app_type] => 1
[patent_app_number] => 6/395342
[patent_app_country] => US
[patent_app_date] => 1982-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 2608
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/528/04528646.pdf
[firstpage_image] =>[orig_patent_app_number] => 395342
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/395342 | Semiconductor memory with selectively enabled precharge and sense amplifier circuits | Jul 5, 1982 | Issued |
Array
(
[id] => 2203818
[patent_doc_number] => 04503523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-05
[patent_title] => 'Dynamic reference potential generating circuit arrangement'
[patent_app_type] => 1
[patent_app_number] => 6/393965
[patent_app_country] => US
[patent_app_date] => 1982-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2946
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/503/04503523.pdf
[firstpage_image] =>[orig_patent_app_number] => 393965
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/393965 | Dynamic reference potential generating circuit arrangement | Jun 29, 1982 | Issued |
Array
(
[id] => 2211491
[patent_doc_number] => 04493056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-01-08
[patent_title] => 'RAM Utilizing offset contact regions for increased storage capacitance'
[patent_app_type] => 1
[patent_app_number] => 6/394055
[patent_app_country] => US
[patent_app_date] => 1982-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5372
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/493/04493056.pdf
[firstpage_image] =>[orig_patent_app_number] => 394055
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/394055 | RAM Utilizing offset contact regions for increased storage capacitance | Jun 29, 1982 | Issued |