Danny Chan

Array ( [id] => 20089506 [patent_doc_number] => 20250219442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => Equipment with Uninterruptible Power Supply to Address Short Power Interruptions [patent_app_type] => utility [patent_app_number] => 19/043507 [patent_app_country] => US [patent_app_date] => 2025-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19043507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009345 [patent_doc_number] => 20250147567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => Methods for Prioritizing Usage of Central Devices for Locating Peripheral Devices [patent_app_type] => utility [patent_app_number] => 18/989806 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18989806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891755 [patent_doc_number] => 20250117067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => MANAGING DELIVERY OF POWER TO PROCESSING ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/922131 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20630879 [patent_doc_number] => 20260095168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => Timing Management in Serial Data Interfaces [patent_app_type] => utility [patent_app_number] => 18/903974 [patent_app_country] => US [patent_app_date] => 2024-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18903974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20680369 [patent_doc_number] => 20260119188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => METHOD AND APPARATUS FOR DISPLAYING BOOT MODE OF PCIE DEVICE, DEVICE, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 19/142147 [patent_app_country] => US [patent_app_date] => 2024-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19142147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19694736 [patent_doc_number] => 20250013281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING POWER AND PERFORMANCE BALANCING BETWEEN MULTIPLE PROCESSING ELEMENTS AND/OR A COMMUNICATION BUS [patent_app_type] => utility [patent_app_number] => 18/890669 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18890669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20221573 [patent_doc_number] => 20250284504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => INTERFACE MODULE, INFORMATION COMMUNICATION DEVICE, AND ACTIVATION METHOD [patent_app_type] => utility [patent_app_number] => 18/882536 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19588193 [patent_doc_number] => 20240385750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/785694 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19756843 [patent_doc_number] => 20250045408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => Systems and Methods for Cryptographically Verifying a User of a Computing Device at the Bootloader Level [patent_app_type] => utility [patent_app_number] => 18/775082 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19694742 [patent_doc_number] => 20250013287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => COORDINATING A CHANGE IN POWER STATE OF A SYSTEM BASIS CHIP WITH A CHANGE IN POWER STATE OF A PHY TRANSCEIVER IMPLEMENTED BY THE SYSTEM BASIS CHIP [patent_app_type] => utility [patent_app_number] => 18/766265 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20805351 [patent_doc_number] => 12670259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Systems and methods for cross operating environment diagnostic operations with context resume [patent_app_type] => utility [patent_app_number] => 18/746353 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3182 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20408593 [patent_doc_number] => 20250377702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => SYSTEMS AND METHODS FOR PROGRAMMING DEVICE MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/740305 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20648079 [patent_doc_number] => 12603029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Power management circuit and timing controller for display device [patent_app_type] => utility [patent_app_number] => 18/650326 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864340 [patent_doc_number] => 20250103126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => UTILIZING DATA MODELING FOR POWER MANAGEMENT OF NETWORK DEVICE COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/650341 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20310548 [patent_doc_number] => 20250328177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => TWO-STAGE PROCESSOR VOLTAGE REGULATION [patent_app_type] => utility [patent_app_number] => 18/643616 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20789934 [patent_doc_number] => 12663849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Data processor core, data processor, electronic device, and storage medium, involving a warm-up state [patent_app_type] => utility [patent_app_number] => 18/636503 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 2361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20289849 [patent_doc_number] => 20250315092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => INTERCONNECT DEVICE POWER ALLOCATION [patent_app_type] => utility [patent_app_number] => 18/627972 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20281756 [patent_doc_number] => 20250306998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => APPARATUS, SYSTEM AND METHOD OF MULTICORE PROCESSOR POWER CONTROL [patent_app_type] => utility [patent_app_number] => 18/620003 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20758080 [patent_doc_number] => 12650850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Method and apparatus for obtaining boot logs, and method for transferring boot logs [patent_app_type] => utility [patent_app_number] => 19/116965 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5407 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19116965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19481665 [patent_doc_number] => 20240329707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => POWER MANAGEMENT FOR MULTIPLE CIRCUIT DOMAINS [patent_app_type] => utility [patent_app_number] => 18/593059 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593059 [rel_patent_id] =>[rel_patent_doc_number] =>)