| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 9585828
[patent_doc_number] => 08775838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-08
[patent_title] => 'Limiting the number of unexpected wakeups in a computer system implementing a power-saving preemptive wakeup method from historical data'
[patent_app_type] => utility
[patent_app_number] => 13/363949
[patent_app_country] => US
[patent_app_date] => 2012-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 6176
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 353
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363949
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/363949 | Limiting the number of unexpected wakeups in a computer system implementing a power-saving preemptive wakeup method from historical data | Jan 31, 2012 | Issued |
Array
(
[id] => 10072310
[patent_doc_number] => 09110668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-18
[patent_title] => 'Enhanced buffer-batch management for energy efficient networking based on a power mode of a network interface'
[patent_app_type] => utility
[patent_app_number] => 13/362966
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8007
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362966
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/362966 | Enhanced buffer-batch management for energy efficient networking based on a power mode of a network interface | Jan 30, 2012 | Issued |
Array
(
[id] => 9826063
[patent_doc_number] => 08935559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'System and method for reducing crosstalk in on-chip networks using a contraflow interconnect and offset repeaters'
[patent_app_type] => utility
[patent_app_number] => 13/360571
[patent_app_country] => US
[patent_app_date] => 2012-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5971
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13360571
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/360571 | System and method for reducing crosstalk in on-chip networks using a contraflow interconnect and offset repeaters | Jan 26, 2012 | Issued |
Array
(
[id] => 8952768
[patent_doc_number] => 20130198549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-01
[patent_title] => 'AUTONOMOUS POWER-GATING DURING IDLE IN A MULTI-CORE SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/360559
[patent_app_country] => US
[patent_app_date] => 2012-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3632
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13360559
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/360559 | Power-gating in a multi-core system without operating system intervention | Jan 26, 2012 | Issued |
Array
(
[id] => 9472414
[patent_doc_number] => 08726060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-13
[patent_title] => 'Semiconductor integrated circuit for transmitting and receiving data signals in a source-synchronous scheme'
[patent_app_type] => utility
[patent_app_number] => 13/342452
[patent_app_country] => US
[patent_app_date] => 2012-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 24
[patent_no_of_words] => 12131
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342452
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/342452 | Semiconductor integrated circuit for transmitting and receiving data signals in a source-synchronous scheme | Jan 2, 2012 | Issued |
Array
(
[id] => 10066394
[patent_doc_number] => 09105249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-11
[patent_title] => 'Energy conservation in a controller using dynamic frequency selection'
[patent_app_type] => utility
[patent_app_number] => 13/340129
[patent_app_country] => US
[patent_app_date] => 2011-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4138
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340129
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/340129 | Energy conservation in a controller using dynamic frequency selection | Dec 28, 2011 | Issued |
Array
(
[id] => 9652206
[patent_doc_number] => 08806243
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-12
[patent_title] => 'Method of and apparatus for energy savings associated with a graphics core'
[patent_app_type] => utility
[patent_app_number] => 13/338354
[patent_app_country] => US
[patent_app_date] => 2011-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5325
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13338354
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/338354 | Method of and apparatus for energy savings associated with a graphics core | Dec 27, 2011 | Issued |
Array
(
[id] => 8524840
[patent_doc_number] => 20120324248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-20
[patent_title] => 'METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING POWER AND PERFORMANCE BALANCING BETWEEN MULTIPLE PROCESSING ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 13/327670
[patent_app_country] => US
[patent_app_date] => 2011-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9107
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13327670
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/327670 | Method, apparatus, and system for energy efficiency and energy conservation including power and performance workload-based balancing between multiple processing elements | Dec 14, 2011 | Issued |
Array
(
[id] => 8863867
[patent_doc_number] => 20130147570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'METHODS AND APPARATUS FOR LOAD INTERROGATION USING POWER USAGE MODULATION'
[patent_app_type] => utility
[patent_app_number] => 13/315317
[patent_app_country] => US
[patent_app_date] => 2011-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4309
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315317
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/315317 | METHODS AND APPARATUS FOR LOAD INTERROGATION USING POWER USAGE MODULATION | Dec 8, 2011 | Abandoned |
Array
(
[id] => 12196701
[patent_doc_number] => 09900448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-20
[patent_title] => 'Technologies for displaying images during a pre-boot phase of a vehicle computing platform'
[patent_app_type] => utility
[patent_app_number] => 13/976612
[patent_app_country] => US
[patent_app_date] => 2011-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4637
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976612
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/976612 | Technologies for displaying images during a pre-boot phase of a vehicle computing platform | Dec 5, 2011 | Issued |
Array
(
[id] => 9378966
[patent_doc_number] => 08683249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-25
[patent_title] => 'Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand'
[patent_app_type] => utility
[patent_app_number] => 13/310892
[patent_app_country] => US
[patent_app_date] => 2011-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5233
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310892
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/310892 | Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand | Dec 4, 2011 | Issued |
Array
(
[id] => 8045967
[patent_doc_number] => 20120072712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-22
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND TELEVISION'
[patent_app_type] => utility
[patent_app_number] => 13/307285
[patent_app_country] => US
[patent_app_date] => 2011-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8062
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0072/20120072712.pdf
[firstpage_image] =>[orig_patent_app_number] => 13307285
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/307285 | Integrated circuit with independently powered processors booted sequentially, while sharing a common memory unit for loading programs onto processors after booting | Nov 29, 2011 | Issued |
Array
(
[id] => 8681553
[patent_doc_number] => 20130049837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-28
[patent_title] => 'SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT HAVING TIME CODE RECEIVER CLOCK SOURCE AND METHOD OF OPERATION THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/297754
[patent_app_country] => US
[patent_app_date] => 2011-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3372
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297754
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/297754 | SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT HAVING TIME CODE RECEIVER CLOCK SOURCE AND METHOD OF OPERATION THEREOF | Nov 15, 2011 | Abandoned |
Array
(
[id] => 8568711
[patent_doc_number] => 20120331282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-27
[patent_title] => 'APPARATUS AND METHODS FOR PEAK POWER MANAGEMENT IN MEMORY SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 13/296898
[patent_app_country] => US
[patent_app_date] => 2011-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6701
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296898
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/296898 | Method and memory system for managing power based on semaphores and timers | Nov 14, 2011 | Issued |
Array
(
[id] => 10650856
[patent_doc_number] => 09367107
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'Method and system for controlling reset state change in a system-on-a-chip device'
[patent_app_type] => utility
[patent_app_number] => 13/276596
[patent_app_country] => US
[patent_app_date] => 2011-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3117
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276596
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/276596 | Method and system for controlling reset state change in a system-on-a-chip device | Oct 18, 2011 | Issued |
Array
(
[id] => 9326199
[patent_doc_number] => 08661236
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Partial initialization of divided programs in response to pre-boot and post-boot activation events to rapidly boot a computer system'
[patent_app_type] => utility
[patent_app_number] => 13/248063
[patent_app_country] => US
[patent_app_date] => 2011-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7549
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248063
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/248063 | Partial initialization of divided programs in response to pre-boot and post-boot activation events to rapidly boot a computer system | Sep 28, 2011 | Issued |
Array
(
[id] => 8735235
[patent_doc_number] => 20130080804
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor'
[patent_app_type] => utility
[patent_app_number] => 13/247580
[patent_app_country] => US
[patent_app_date] => 2011-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4070
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247580
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/247580 | Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin | Sep 27, 2011 | Issued |
Array
(
[id] => 9665882
[patent_doc_number] => 08812891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Image forming apparatus with motor drivers capable of directly communicating power abnormalities to other drivers'
[patent_app_type] => utility
[patent_app_number] => 13/247904
[patent_app_country] => US
[patent_app_date] => 2011-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9065
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 577
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247904
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/247904 | Image forming apparatus with motor drivers capable of directly communicating power abnormalities to other drivers | Sep 27, 2011 | Issued |
Array
(
[id] => 10890637
[patent_doc_number] => 08914650
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Dynamically adjusting power of non-core processor circuitry including buffer circuitry'
[patent_app_type] => utility
[patent_app_number] => 13/247594
[patent_app_country] => US
[patent_app_date] => 2011-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5511
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247594
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/247594 | Dynamically adjusting power of non-core processor circuitry including buffer circuitry | Sep 27, 2011 | Issued |
Array
(
[id] => 8735234
[patent_doc_number] => 20130080803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'Estimating Temperature Of A Processor Core In A Low Power State'
[patent_app_type] => utility
[patent_app_number] => 13/247564
[patent_app_country] => US
[patent_app_date] => 2011-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5133
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247564
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/247564 | Estimating temperature of a processor core in a low power state without thermal sensor information | Sep 27, 2011 | Issued |