Search

Danny Hong

Examiner (ID: 2133, Phone: (571)270-5107 , Office: P/3727 )

Most Active Art Unit
3727
Art Unit(s)
3727, 3723
Total Applications
485
Issued Applications
270
Pending Applications
0
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17085776 [patent_doc_number] => 20210280783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/329247 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329247
Step height mitigation in resistive random access memory structures May 24, 2021 Issued
Array ( [id] => 17053934 [patent_doc_number] => 20210263368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/317890 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317890
DISPLAY DEVICE May 11, 2021 Abandoned
Array ( [id] => 17941696 [patent_doc_number] => 11476155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Patterning method [patent_app_type] => utility [patent_app_number] => 17/237699 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 12000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237699
Patterning method Apr 21, 2021 Issued
Array ( [id] => 17158982 [patent_doc_number] => 20210320033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/225450 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225450
Method of manufacturing semiconductor device Apr 7, 2021 Issued
Array ( [id] => 20267039 [patent_doc_number] => 12438038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Forming vias in a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/223876 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223876
Forming vias in a semiconductor device Apr 5, 2021 Issued
Array ( [id] => 18379795 [patent_doc_number] => 20230154884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => Ag ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/916935 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17916935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/916935
AG alloy bonding wire for semiconductor devices and semiconductor device Mar 28, 2021 Issued
Array ( [id] => 20484243 [patent_doc_number] => 12532724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Preventing electrode discontinuation on microdevice sidewall [patent_app_type] => utility [patent_app_number] => 17/913391 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17913391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/913391
Preventing electrode discontinuation on microdevice sidewall Mar 22, 2021 Issued
Array ( [id] => 17893270 [patent_doc_number] => 11456252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Semiconductor device having symmetric conductive interconnection patterns [patent_app_type] => utility [patent_app_number] => 17/189839 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189839
Semiconductor device having symmetric conductive interconnection patterns Mar 1, 2021 Issued
Array ( [id] => 19900244 [patent_doc_number] => 12278181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Integrated circuits including via array and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/188414 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7094 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/188414
Integrated circuits including via array and methods of manufacturing the same Feb 28, 2021 Issued
Array ( [id] => 16888997 [patent_doc_number] => 20210175194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING [patent_app_type] => utility [patent_app_number] => 17/174827 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174827
Bond pad with micro-protrusions for direct metallic bonding Feb 11, 2021 Issued
Array ( [id] => 18319501 [patent_doc_number] => 20230117629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => IMAGING ELEMENT AND METHOD FOR MANUFACTURING IMAGING ELEMENT [patent_app_type] => utility [patent_app_number] => 17/914038 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/914038
IMAGING ELEMENT AND METHOD FOR MANUFACTURING IMAGING ELEMENT Feb 9, 2021 Pending
Array ( [id] => 18704687 [patent_doc_number] => 11791204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Semiconductor device with connecting structure having a doped layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/171210 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171210
Semiconductor device with connecting structure having a doped layer and method for forming the same Feb 8, 2021 Issued
Array ( [id] => 18073747 [patent_doc_number] => 11532587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Method for manufacturing semiconductor package with connection structures including via groups [patent_app_type] => utility [patent_app_number] => 17/170268 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 52 [patent_no_of_words] => 7809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170268
Method for manufacturing semiconductor package with connection structures including via groups Feb 7, 2021 Issued
Array ( [id] => 17010991 [patent_doc_number] => 20210242152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SELECTIVE ALTERATION OF INTERCONNECT PADS FOR DIRECT BONDING [patent_app_type] => utility [patent_app_number] => 17/168034 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168034
SELECTIVE ALTERATION OF INTERCONNECT PADS FOR DIRECT BONDING Feb 3, 2021 Pending
Array ( [id] => 20540542 [patent_doc_number] => 12557631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Low-resistance copper interconnects [patent_app_type] => utility [patent_app_number] => 17/248594 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 17131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248594
Low-resistance copper interconnects Jan 28, 2021 Issued
Array ( [id] => 16781752 [patent_doc_number] => 20210118831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR DEVICE BONDING AREA INCLUDING FUSED SOLDER FILM AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/137657 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137657
Semiconductor device bonding area including fused solder film and manufacturing method Dec 29, 2020 Issued
Array ( [id] => 18031961 [patent_doc_number] => 11515159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Forming contact holes using litho-etch-litho-etch approach [patent_app_type] => utility [patent_app_number] => 17/137320 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137320
Forming contact holes using litho-etch-litho-etch approach Dec 28, 2020 Issued
Array ( [id] => 17676651 [patent_doc_number] => 20220189818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ULTRALOW-K DIELECTRIC-GAP WRAPPED CONTACTS AND METHOD [patent_app_type] => utility [patent_app_number] => 17/118697 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118697
Ultralow-K dielectric-gap wrapped contacts and method Dec 10, 2020 Issued
Array ( [id] => 16765728 [patent_doc_number] => 20210111310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/106990 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106990
LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE Nov 29, 2020 Abandoned
Array ( [id] => 17262684 [patent_doc_number] => 20210375669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SURFACE UNIFORMITY CONTROL IN PIXEL STRUCTURES OF IMAGE SENSORS [patent_app_type] => utility [patent_app_number] => 17/102623 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102623
Surface uniformity control in pixel structures of image sensors Nov 23, 2020 Issued
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