Search

Danny Nguyen

Examiner (ID: 5552, Phone: (571)272-2054 , Office: P/2836 )

Most Active Art Unit
2836
Art Unit(s)
2836, 2838, 2663, 2739
Total Applications
2295
Issued Applications
1999
Pending Applications
110
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20119758 [patent_doc_number] => 12369499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Magnetoresistive random access memory and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/582684 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582684 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582684
Magnetoresistive random access memory and method of manufacturing the same Feb 20, 2024 Issued
Array ( [id] => 19407248 [patent_doc_number] => 20240290759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/582905 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582905
SEMICONDUCTOR DEVICE Feb 20, 2024 Pending
Array ( [id] => 19237470 [patent_doc_number] => 20240194665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/443779 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443779
Semiconductor chip, semiconductor device and manufacturing method of semiconductor device Feb 15, 2024 Issued
Array ( [id] => 20332830 [patent_doc_number] => 12463115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Electrostatic discharge protection circuit [patent_app_type] => utility [patent_app_number] => 18/442671 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 1095 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442671 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442671
Electrostatic discharge protection circuit Feb 14, 2024 Issued
Array ( [id] => 19546560 [patent_doc_number] => 20240363596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/415183 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415183
DISPLAY DEVICE Jan 16, 2024 Pending
Array ( [id] => 19407296 [patent_doc_number] => 20240290807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SUBSTRATELESS CHIP SCALE OPTICAL SENSOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/415231 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415231
SUBSTRATELESS CHIP SCALE OPTICAL SENSOR PACKAGE Jan 16, 2024 Pending
Array ( [id] => 19161243 [patent_doc_number] => 20240153950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/413869 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413869
Semiconductor device including transistors sharing gates with structures having reduced parasitic circuit Jan 15, 2024 Issued
Array ( [id] => 20375328 [patent_doc_number] => 12482772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Bonding structure of dies with dangling bonds [patent_app_type] => utility [patent_app_number] => 18/411674 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 2080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411674
Bonding structure of dies with dangling bonds Jan 11, 2024 Issued
Array ( [id] => 20096415 [patent_doc_number] => 20250226351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => SEMICONDUCTOR PACKAGE WITH HEAT FLOW RESTRICTING CONNECTOR [patent_app_type] => utility [patent_app_number] => 18/407918 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407918
SEMICONDUCTOR PACKAGE WITH HEAT FLOW RESTRICTING CONNECTOR Jan 8, 2024 Pending
Array ( [id] => 19161174 [patent_doc_number] => 20240153881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => System on Integrated Chips (SoIC) and Semiconductor Structures with Integrated SoIC [patent_app_type] => utility [patent_app_number] => 18/402061 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402061
System on Integrated Chips (SoIC) and Semiconductor Structures with Integrated SoIC Jan 1, 2024 Pending
Array ( [id] => 19539522 [patent_doc_number] => 12132079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Bonding and isolation techniques for stacked transistor structures [patent_app_type] => utility [patent_app_number] => 18/392379 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 21266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/392379
Bonding and isolation techniques for stacked transistor structures Dec 20, 2023 Issued
Array ( [id] => 20074237 [patent_doc_number] => 20250212459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/391056 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/391056
METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS Dec 19, 2023 Pending
Array ( [id] => 19071294 [patent_doc_number] => 20240105720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/525909 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525909 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525909
Semiconductor device and method for fabricating the same Nov 30, 2023 Issued
Array ( [id] => 19206155 [patent_doc_number] => 20240178054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING A DEEP TRENCH INSULATION AND MANUFACTURING PROCESS [patent_app_type] => utility [patent_app_number] => 18/520894 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520894
HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING A DEEP TRENCH INSULATION AND MANUFACTURING PROCESS Nov 27, 2023 Pending
Array ( [id] => 20028943 [patent_doc_number] => 20250167165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SYSTEM INCLUDING A PLURALITY OF DIE HEADS WITH RELEASABLY COUPLED DIE CHUCKS AND A METHOD OF USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/516370 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516370 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516370
SYSTEM INCLUDING A PLURALITY OF DIE HEADS WITH RELEASABLY COUPLED DIE CHUCKS AND A METHOD OF USING THE SAME Nov 20, 2023 Pending
Array ( [id] => 20028856 [patent_doc_number] => 20250167078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEMICONDUCTOR DIE INCLUDING FUSE STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/514243 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514243
SEMICONDUCTOR DIE INCLUDING FUSE STRUCTURE AND METHODS FOR FORMING THE SAME Nov 19, 2023 Pending
Array ( [id] => 20021775 [patent_doc_number] => 20250159997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => ENLARGED BOTTOM CONTACT AREA IN STACKED TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/509382 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509382
ENLARGED BOTTOM CONTACT AREA IN STACKED TRANSISTORS Nov 14, 2023 Pending
Array ( [id] => 19023237 [patent_doc_number] => 20240079408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/508015 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508015
SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT Nov 12, 2023 Pending
Array ( [id] => 20011235 [patent_doc_number] => 20250149457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/500933 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500933
ELECTRONIC DEVICE Nov 1, 2023 Pending
Array ( [id] => 19255177 [patent_doc_number] => 20240206174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/498696 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498696
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME Oct 30, 2023 Pending
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