
Dao H. Nguyen
Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2283 |
| Issued Applications | 1976 |
| Pending Applications | 142 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 717174
[patent_doc_number] => 07053476
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-30
[patent_title] => 'Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages'
[patent_app_type] => utility
[patent_app_number] => 10/632553
[patent_app_country] => US
[patent_app_date] => 2003-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 12026
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/053/07053476.pdf
[firstpage_image] =>[orig_patent_app_number] => 10632553
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/632553 | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages | Aug 1, 2003 | Issued |
Array
(
[id] => 734137
[patent_doc_number] => 07038272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-02
[patent_title] => 'Method for forming a channel zone of a transistor and NMOS transistor'
[patent_app_type] => utility
[patent_app_number] => 10/631350
[patent_app_country] => US
[patent_app_date] => 2003-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3657
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/038/07038272.pdf
[firstpage_image] =>[orig_patent_app_number] => 10631350
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/631350 | Method for forming a channel zone of a transistor and NMOS transistor | Jul 30, 2003 | Issued |
Array
(
[id] => 686732
[patent_doc_number] => 07078349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-18
[patent_title] => 'Method to form self-aligned floating gate to diffusion structures in flash'
[patent_app_type] => utility
[patent_app_number] => 10/631842
[patent_app_country] => US
[patent_app_date] => 2003-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_no_of_words] => 2727
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/078/07078349.pdf
[firstpage_image] =>[orig_patent_app_number] => 10631842
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/631842 | Method to form self-aligned floating gate to diffusion structures in flash | Jul 30, 2003 | Issued |
Array
(
[id] => 7459647
[patent_doc_number] => 20040094844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Multichip module and multichip shutdown method'
[patent_app_type] => new
[patent_app_number] => 10/631639
[patent_app_country] => US
[patent_app_date] => 2003-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4624
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20040094844.pdf
[firstpage_image] =>[orig_patent_app_number] => 10631639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/631639 | Multichip module and multichip shutdown method | Jul 30, 2003 | Issued |
Array
(
[id] => 7267758
[patent_doc_number] => 20040056276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Method and device using titanium doped aluminum oxide for passivation of ferroelectric materials'
[patent_app_type] => new
[patent_app_number] => 10/621850
[patent_app_country] => US
[patent_app_date] => 2003-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3581
[patent_no_of_claims] => 24
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20040056276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10621850
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/621850 | Method and device using titanium doped aluminum oxide for passivation of ferroelectric materials | Jul 15, 2003 | Issued |
Array
(
[id] => 624006
[patent_doc_number] => 07138716
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-21
[patent_title] => 'Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power'
[patent_app_type] => utility
[patent_app_number] => 10/607550
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/138/07138716.pdf
[firstpage_image] =>[orig_patent_app_number] => 10607550
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/607550 | Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power | Jun 26, 2003 | Issued |
Array
(
[id] => 7404709
[patent_doc_number] => 20040262683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'PMOS transistor strain optimization with raised junction regions'
[patent_app_type] => new
[patent_app_number] => 10/608870
[patent_app_country] => US
[patent_app_date] => 2003-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7286
[patent_no_of_claims] => 24
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[pdf_file] => publications/A1/0262/20040262683.pdf
[firstpage_image] =>[orig_patent_app_number] => 10608870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/608870 | PMOS transistor strain optimization with raised junction regions | Jun 26, 2003 | Abandoned |
Array
(
[id] => 6823810
[patent_doc_number] => 20030234432
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'Image sensor and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/464340
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7464
[patent_no_of_claims] => 58
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20030234432.pdf
[firstpage_image] =>[orig_patent_app_number] => 10464340
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/464340 | Image sensor and method of fabricating the same | Jun 17, 2003 | Issued |
Array
(
[id] => 7253330
[patent_doc_number] => 20040259378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'METHODS AND DEVICES FOR THE SUPPRESSION OF COPPER HILLOCK FORMATION'
[patent_app_type] => new
[patent_app_number] => 10/465389
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4962
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[pdf_file] => publications/A1/0259/20040259378.pdf
[firstpage_image] =>[orig_patent_app_number] => 10465389
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/465389 | Methods and devices for the suppression of copper hillock formation | Jun 17, 2003 | Issued |
Array
(
[id] => 7304863
[patent_doc_number] => 20040140498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Dual-bit nitride read only memory cell'
[patent_app_type] => new
[patent_app_number] => 10/460239
[patent_app_country] => US
[patent_app_date] => 2003-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1817
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[pdf_file] => publications/A1/0140/20040140498.pdf
[firstpage_image] =>[orig_patent_app_number] => 10460239
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/460239 | Dual-bit nitride read only memory cell | Jun 12, 2003 | Abandoned |
Array
(
[id] => 7296595
[patent_doc_number] => 20040214440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Methods of forming patterns for semiconductor constructions; and molds configured to pattern masses associated with semiconductor constructions'
[patent_app_type] => new
[patent_app_number] => 10/461811
[patent_app_country] => US
[patent_app_date] => 2003-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0214/20040214440.pdf
[firstpage_image] =>[orig_patent_app_number] => 10461811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/461811 | Molds configured to pattern masses associated with semiconductor constructions | Jun 11, 2003 | Issued |
Array
(
[id] => 1175722
[patent_doc_number] => 06750485
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-15
[patent_title] => 'Lock in pinned photodiode photodetector'
[patent_app_type] => B2
[patent_app_number] => 10/459595
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[pdf_file] => patents/06/750/06750485.pdf
[firstpage_image] =>[orig_patent_app_number] => 10459595
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/459595 | Lock in pinned photodiode photodetector | Jun 11, 2003 | Issued |
Array
(
[id] => 996837
[patent_doc_number] => 06914279
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[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Multifunctional biosensor based on ZnO nanostructures'
[patent_app_type] => utility
[patent_app_number] => 10/456050
[patent_app_country] => US
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[pdf_file] => patents/06/914/06914279.pdf
[firstpage_image] =>[orig_patent_app_number] => 10456050
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/456050 | Multifunctional biosensor based on ZnO nanostructures | Jun 5, 2003 | Issued |
Array
(
[id] => 1102940
[patent_doc_number] => 06811471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-02
[patent_title] => 'Abrasive particles to clean semiconductor wafers during chemical mechanical planarization'
[patent_app_type] => B2
[patent_app_number] => 10/455129
[patent_app_country] => US
[patent_app_date] => 2003-06-05
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[firstpage_image] =>[orig_patent_app_number] => 10455129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/455129 | Abrasive particles to clean semiconductor wafers during chemical mechanical planarization | Jun 4, 2003 | Issued |
Array
(
[id] => 5175118
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[patent_title] => 'Semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 10453940
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453940 | Semiconductor device | Jun 3, 2003 | Issued |
Array
(
[id] => 1152790
[patent_doc_number] => 06770907
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[patent_issue_date] => 2004-08-03
[patent_title] => 'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'
[patent_app_type] => B2
[patent_app_number] => 10/449426
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/449426 | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure | May 29, 2003 | Issued |
Array
(
[id] => 6662145
[patent_doc_number] => 20030201471
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[patent_title] => 'Localized array threshold voltage implant to enhance charge storage within DRAM memory cells'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/437592 | Kill index analysis for automatic defect classification in semiconductor wafers | May 12, 2003 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/436419 | Method of fabricating a semiconductor component | May 11, 2003 | Abandoned |
Array
(
[id] => 1091130
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[patent_title] => 'Charge control of micro-electromechanical device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/428168 | Charge control of micro-electromechanical device | Apr 29, 2003 | Issued |